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* Initialize pcids array for the proc0 pmap.Konstantin Belousov2015-05-101-0/+5
* Tweak assert to also print the thread address.Konstantin Belousov2015-05-101-2/+2
* On exec, single-threading must be enforced before arguments space isKonstantin Belousov2015-05-101-1/+9
* Correct the assertion. We should compare the pmap' curcpu pcid valueKonstantin Belousov2015-05-091-1/+2
* Rewrite amd64 PCID implementation to follow an algorithm described inKonstantin Belousov2015-05-0911-478/+258
* Remove unused define.Konstantin Belousov2015-05-091-2/+0
* If x86 CPU implementation of the MWAIT instruction reasonablyKonstantin Belousov2015-05-092-7/+1
* Check 'td_owepreempt' and yield the vcpu thread if it is set.Neel Natu2015-05-061-1/+7
* Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup().Neel Natu2015-05-065-93/+88
* Do a proper emulation of guest writes to MSR_EFER.Neel Natu2015-05-063-14/+128
* Emulate the 'CMP r/m8, imm8' instruction encountered when booting a WindowsNeel Natu2015-05-041-2/+14
* Don't advertise the Intel SMX capability to the guest.Neel Natu2015-05-021-1/+2
* Emulate machine check related MSRs to allow guest OSes like Windows to boot.Neel Natu2015-05-023-7/+24
* r281630 relaxed the limits on the vectors that can be asserted in the IRRs.Neel Natu2015-05-011-11/+9
* Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs areNeel Natu2015-05-011-0/+2
* Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.Neel Natu2015-04-3014-20/+4
* When an instruction cannot be decoded just return to userspace so bhyve(8)Neel Natu2015-04-301-2/+6
* Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.Neel Natu2015-04-303-3/+38
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsJohn Baldwin2015-04-303-297/+0
* Re-implement RTC current time calculation to eliminate the possibility ofNeel Natu2015-04-291-21/+32
* Microsoft vmbus, storage and other related driver enhancements for HyperV.Wei Hu2015-04-293-1/+21
* Emulate the 'bit test' instruction. Windows 7 uses 'bit test' to check theNeel Natu2015-04-291-0/+52
* Implement the century byte in the RTC. Some guests require this field to beNeel Natu2015-04-281-22/+44
* STOS/STOSB/STOSW/STOSD/STOSQ instruction emulation.Tycho Nightingale2015-04-251-0/+77
* Move common code from sys/i386/i386/mp_machdep.c andKonstantin Belousov2015-04-242-1022/+51
* Reassign copyright statements on several files from AdvancedJohn Baldwin2015-04-231-1/+1
* Missing break in switch case.Marcelo Araujo2015-04-231-0/+1
* Move some common code from sys/amd64/amd64/machdep.c andKonstantin Belousov2015-04-222-369/+1
* Remove duplicate definitions of MWAIT_CX hints. Identical defines inKonstantin Belousov2015-04-201-9/+0
* Remove lazy pmap switch code from i386. Naive benchmark with md(4)Konstantin Belousov2015-04-181-0/+2
* Relax the check on which vectors can be delivered through the APIC. AccordingNeel Natu2015-04-161-1/+5
* Prefer 'vcpu_should_yield()' over checking 'curthread->td_flags' directly.Neel Natu2015-04-161-1/+1
* Use explicitly sized types in EFI module metadataEd Maste2015-04-101-5/+5
* Enhance the support for Group 1 Extended opcodes:Tycho Nightingale2015-04-061-38/+84
* adrian asked me to revert and get more testingEitan Adler2015-04-051-5/+1
* head/sys/amd64/amd64/support.S: unroll loopEitan Adler2015-04-051-1/+5
* Fix integer truncation bug in malloc(9)Ryan Stone2015-04-011-2/+2
* Fix "MOVS" instruction memory to MMIO emulation. Currently updates toTycho Nightingale2015-04-014-35/+54
* Provide workaround for a performance issue with the popcnt instructionKonstantin Belousov2015-03-311-17/+24
* Wait 100 microseconds for a local APIC to dispatch each startup-related IPIJohn Baldwin2015-03-301-3/+3
* Make it possible for the signal handler to act on #ss. Load theKonstantin Belousov2015-03-281-0/+1
* The #ss fault handler erronously does not check for the faultKonstantin Belousov2015-03-281-2/+0
* Fix the RTC device model to operate correctly in 12-hour mode. The followingNeel Natu2015-03-281-6/+41
* When fetching an instruction in non-64bit mode, consider the value of theTycho Nightingale2015-03-245-6/+20
* Use VT-d interrupt remapping block (IR) to perform FSB messagesKonstantin Belousov2015-03-191-0/+2
* Update to the Intel ixgbe driver:Jack F Vogel2015-03-171-1/+2
* Report ARAT (APIC-Timer-always-running) feature for virtual CPU.Alexander Motin2015-03-161-0/+6
* Use lapic_ipi_alloc() to dynamically allocate IPI slots needed by bhyve whenNeel Natu2015-03-1410-184/+40
* Only schedule interrupts on a single hyperthread of a modern Intel CPU coreJohn Baldwin2015-03-061-2/+2
* When ICW1 is issued the edge sense circuit is reset which means thatTycho Nightingale2015-03-061-0/+1
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