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| author | Tycho Nightingale <tychon@FreeBSD.org> | 2015-03-06 02:05:45 +0000 |
|---|---|---|
| committer | Tycho Nightingale <tychon@FreeBSD.org> | 2015-03-06 02:05:45 +0000 |
| commit | 76b3c718be824fb13fae4e2e232ae2425ef81fd8 (patch) | |
| tree | bc897a7649522aaded67d9f58c32172c00970ef1 /sys/amd64 | |
| parent | 8e01fdea2bf6e59a50fb0023bd8b24261dcdd980 (diff) | |
| download | src-76b3c718be824fb13fae4e2e232ae2425ef81fd8.tar.gz src-76b3c718be824fb13fae4e2e232ae2425ef81fd8.zip | |
When ICW1 is issued the edge sense circuit is reset which means that
following an initialization a low-to-high transistion is necesary to
generate an interrupt.
Reviewed by: neel
Notes
Notes:
svn path=/head/; revision=279683
Diffstat (limited to 'sys/amd64')
| -rw-r--r-- | sys/amd64/vmm/io/vatpic.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/amd64/vmm/io/vatpic.c b/sys/amd64/vmm/io/vatpic.c index 328c35f700b8..0df6e7c68081 100644 --- a/sys/amd64/vmm/io/vatpic.c +++ b/sys/amd64/vmm/io/vatpic.c @@ -275,6 +275,7 @@ vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val) atpic->ready = false; atpic->icw_num = 1; + atpic->request = 0; atpic->mask = 0; atpic->lowprio = 7; atpic->rd_cmd_reg = 0; |