aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/DirectX/DXILStubs.td
blob: ce4327f93bc18cee08136fcf7de3158870d0b977 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
// DXIL doesn't actually use registers, but this gets the boilerplate code
// generated through tablegen.
let Namespace = "DXIL" in {
def DXIL : Register<"DXIL">;
def DXILClass : RegisterClass<"DXIL", [i32], 32, (add DXIL)>;
}

class DXILInst : Instruction {
  let Namespace = "DXIL";
  let DecoderNamespace = "DXIL";

  dag OutOperandList = (outs);
  dag InOperandList =  (ins);
  let AsmString = "dummy";
  let Pattern = [];
}

def DummyInst : DXILInst;