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* riscv: default to non-executable stackEd Maste2019-02-061-1/+1
* Follow arm[32] and sparc64 KAPI and provide the FreeBSD standard spellingDavid E. O'Brien2019-01-291-0/+2
* Remove a redundant test.Mark Johnston2019-01-281-1/+1
* Optimize RISC-V copyin(9)/copyout(9) routines.Mark Johnston2019-01-212-9/+44
* Deduplicate common code in copyin()/copyout() with a macro.Mark Johnston2019-01-211-27/+28
* Don't enable interrupts in init_secondary().Mark Johnston2019-01-041-4/+0
* Fix dirty bit handling in pmap_remove_write().Mark Johnston2019-01-041-6/+4
* Clear PGA_WRITEABLE in pmap_remove_pages().Mark Johnston2019-01-041-0/+3
* Fix a use-after-free in the riscv pmap_release() implementation.Mark Johnston2019-01-031-7/+3
* Synchronize access to the allpmaps list.Mark Johnston2019-01-031-1/+9
* Fix some issues with the riscv pmap_protect() implementation.Mark Johnston2019-01-031-16/+26
* Set PTE_U on PTEs created by pmap_enter_quick().Mark Johnston2019-01-031-13/+8
* Use regular stores to update PTEs in the riscv pmap layer.Mark Johnston2019-01-031-43/+30
* Configure hz=100 in the QEMU target.Mark Johnston2019-01-031-0/+1
* Remove iBCS2, part2: general kernelMateusz Guzik2018-12-192-3/+0
* Replace uses of sbadaddr with stval.Mark Johnston2018-12-195-15/+15
* Implement cpu_halt() for RISC-V.Mark Johnston2018-12-191-1/+3
* Add some more checking to the RISC-V page fault handler.Mark Johnston2018-12-141-18/+22
* Avoid needless TLB invalidations in pmap_remove_pages().Mark Johnston2018-12-141-5/+5
* Assume that pmap_l1() will return a PTE.Mark Johnston2018-12-141-2/+0
* Add a QEMU config for RISC-V.Mark Johnston2018-12-141-0/+9
* Enable witness(4) in the RISC-V GENERIC config.Mark Johnston2018-12-141-1/+1
* Clean up the riscv pmap_bootstrap() implementation.Mark Johnston2018-12-141-87/+29
* Remove an unused malloc(9) type.Mark Johnston2018-12-111-2/+0
* Use inline tests for individual PTE bits in the RISC-V pmap.Mark Johnston2018-12-111-51/+20
* Update the description of the address space layout on RISC-V.Mark Johnston2018-12-071-15/+14
* Rename sptbr to satp per v1.10 of the privileged architecture spec.Mark Johnston2018-12-074-5/+12
* Fix reporting of SS_ONSTACKEric van Gyzen2018-11-301-2/+2
* Prevent kernel stack disclosure in signal deliveryEric van Gyzen2018-11-261-0/+1
* RISC-V: Implement get_cyclecount(9).Mark Johnston2018-11-131-2/+2
* RISC-V: Add macros for reading performance counter CSRs.Mark Johnston2018-11-132-0/+24
* Drop the legacy ELF brandinfo for the old rtld from arm64 and riscv.John Baldwin2018-11-071-16/+0
* Enable use of a global shared page for RISC-V.John Baldwin2018-11-071-1/+3
* Add a KPI for the delay while spinning on a spin lock.John Baldwin2018-11-051-0/+1
* Rework setting PTE_D for kernel mappings.John Baldwin2018-11-051-3/+10
* Restrict setting PTE execute permissions on RISC-V.John Baldwin2018-11-014-10/+17
* Set PTE_A and PTE_D for user mappings in pmap_enter().John Baldwin2018-11-011-3/+5
* SBI calls expect a pointer to a u_long rather than a pointer.John Baldwin2018-11-012-3/+3
* Don't allow debuggers to modify SSTATUS, only to read it.John Baldwin2018-11-011-1/+0
* Implement ptrace_set_pc() and fail PT_*STEP requests explicitly.John Baldwin2018-11-011-3/+3
* Compile in VERBOSE_SYSINIT support by default, remain silent by defaultKyle Evans2018-10-311-1/+1
* o Add pmap lock around pmap_fault_fixup() to ensure other thread will notRuslan Bukin2018-10-261-4/+15
* Consolidate identical ELF auxargs type defintions.Brooks Davis2018-10-221-31/+0
* Support RISC-V implementations that do not manage the A and D bitsRuslan Bukin2018-10-185-12/+54
* Revert r339421 due to unintended files included to commit.Ruslan Bukin2018-10-185-54/+12
* Support RISC-V implementations that do not manage the A and D bitsRuslan Bukin2018-10-185-12/+54
* Invalidate TLB on a local hart.Ruslan Bukin2018-10-161-0/+1
* Various fixes for TLB management on RISC-V.John Baldwin2018-10-157-196/+156
* Initialize interrupt priority to 0 on all sources.Ruslan Bukin2018-10-121-0/+1
* Add support for the UART device found in lowRISC system-on-a-chip.Ruslan Bukin2018-10-121-0/+1
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