| Commit message (Collapse) | Author | Age | Files | Lines |
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Remove sys/mips as the next step of decomissioning mips from the tree.
Remove mips special cases from the kernel make files. Remove the mips
specific linker scripts.
Sponsored by: Netflix
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Obtained from: CheriBSD
Sponsored by: DARPA, AFRL
Notes:
svn path=/head/; revision=332441
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Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30
Add kernel side support for large TLB on BERI/CHERI.
Modelled similar to NLM
MFC after: 3 days
Sponsored by: DAPRA/AFRL
Notes:
svn path=/head/; revision=256935
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Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.
Sponsored by: DARPA, AFRL
Notes:
svn path=/head/; revision=239671
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