aboutsummaryrefslogtreecommitdiff
path: root/sys/arm64/include/armreg.h
Commit message (Expand)AuthorAgeFilesLines
* arm64: Don't enable interrupts when in a spinlockAndrew Turner5 hours1-0/+1
* arm64: Decode CTR_EL0 via a tableAndrew Turner3 days1-0/+11
* arm64: Add ID register field width valuesAndrew Turner3 days1-0/+157
* arm64: Remove old I-Cache typesAndrew Turner3 days1-2/+0
* arm64: Enable SVE in userspaceAndrew Turner2024-09-301-0/+1
* arm64: Initial SVE supportAndrew Turner2024-09-301-0/+7
* arm64: Add support for FIQsAyrton Munoz2024-09-221-2/+2
* arm64: Remove TCR_CACHE_ATTRS and TCR_SMP_ATTRSAndrew Turner2024-09-051-8/+0
* arm64: Add the tcr_el2 ds fieldAndrew Turner2024-09-051-0/+2
* arm64: Fix the ESR_EL1_op2 valueAndrew Turner2024-08-291-1/+1
* arm64: Add counter timer registers to armreg.hAndrew Turner2024-08-201-0/+48
* arm64: Add EL1 and EL12 register alt namesAndrew Turner2024-07-231-0/+222
* arm64: Fix indentation to be consistentAndrew Turner2024-06-101-7/+7
* arm64: Add the pointer auth registers to armreg.hAndrew Turner2024-05-221-0/+80
* arm64: Use the UL macro in TCR_EL1 definesAndrew Turner2024-05-221-48/+48
* arm64: add CONTEXTIDR_EL1 regZachary Leaf2024-05-171-0/+9
* arm64: add PMBSR_MSS_{BSC,FSC} status code fieldZachary Leaf2024-05-171-0/+2
* arm64: make SPE regs use ALT_NAME macroZachary Leaf2024-05-171-60/+72
* arm64: Add MRS_REG_ALT_NAME ID register macrosAndrew Turner2024-05-171-0/+15
* arm64: Add EL1 hardware breakpoint exceptionsAndrew Turner2024-03-211-0/+1
* arm64: Add ISS_MSR_REG for ESR_ELx.ISS valuesAndrew Turner2024-02-211-0/+6
* arm64: Add more spsr_el1 register valuesAndrew Turner2024-02-211-0/+7
* arm64: Add CurrentEL register definitionsAndrew Turner2024-02-211-0/+8
* armv8rng: Don't require toolchain to support FEAT_RNGJessica Clarke2023-12-011-0/+9
* Add BTI exceptionsAndrew Turner2023-09-221-0/+1
* arm64: Add TCR register masksAndrew Turner2023-09-081-1/+4
* arm64: Fix the TCR_TBI0 macro to use ULAndrew Turner2023-09-081-1/+1
* arm64: Fix the TCR_EPD0 definitionAndrew Turner2023-09-061-1/+1
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
* arm64: Add constants for decoding ISS fields for WF* exceptionsMark Johnston2023-07-281-0/+20
* arm64: Decode the ID_AA64PFR2_EL1 registerAndrew Turner2023-07-281-0/+8
* arm64: Update the ID_AA64PFR1_EL1 fieldsAndrew Turner2023-07-281-9/+37
* arm64: Update the ID_AA64PFR0_EL1 fieldsAndrew Turner2023-07-281-5/+12
* arm64: Decode the ID_AA64MMFR4_EL1 registerAndrew Turner2023-07-281-0/+8
* arm64: Decode the ID_AA64MMFR3_EL1 registerAndrew Turner2023-07-281-0/+28
* arm64: Don't use hex for ID_AA64MMFR2_EL1_op/CR*Andrew Turner2023-07-281-5/+5
* arm64: Update the ID_AA64MMFR1_EL1 fieldsAndrew Turner2023-07-281-0/+36
* arm64: Update the ID_AA64MMFR0_EL1 fieldsAndrew Turner2023-07-281-10/+25
* arm64: Update the ID_AA64ISAR1_EL1 fieldsAndrew Turner2023-07-281-5/+18
* arm64: Update the ID_AA64ISAR0_EL1 fieldsAndrew Turner2023-07-281-5/+9
* arm64: Update the ID_AA64DFR0_EL1 fieldsAndrew Turner2023-07-281-6/+38
* arm64 lib32: prepare arm64 headers to redirect to armMike Karels2023-07-251-0/+6
* Add more arm64 special register valuesAndrew Turner2023-06-121-0/+16
* arm64: Fix the definition of ID_AA64DFR1_EL1Andrew Turner2023-06-021-1/+1
* Add more arm64 ID registersAndrew Turner2023-06-021-0/+16
* arm64: Remove CNTHCTL_EL2 from arm64.hAndrew Turner2023-05-241-7/+0
* Add more arm64 special registersAndrew Turner2023-05-241-2/+46
* Mark the arm64 PSR register fields with ULAndrew Turner2023-03-231-23/+23
* Mark arm64 mair_el1 fields as unsigned longAndrew Turner2023-03-161-6/+6
* Decode the arm64 ID_AA64ISAR1_EL1 registerAndrew Turner2022-09-061-0/+47
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-24 15:20:34 +0000