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path: root/sys/arm/include/cpufunc.h
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* Eliminate an unused macro whose name clashes now with a function in theIan Lepore2014-12-281-1/+0
* Delete obsolete and unused PJ4B CPU functionsZbigniew Bodek2014-05-251-9/+0
* Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().Ian Lepore2014-05-111-0/+2
* Make this declaration into a proper function prototype.Ian Lepore2014-04-291-1/+1
* Provide a proper armv7 implementation of icache_sync_all rather thanIan Lepore2014-04-271-0/+1
* Remove all traces of support for ARM chips prior to the arm9 series. WeIan Lepore2014-03-091-106/+0
* Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementationIan Lepore2014-02-281-0/+1
* Add a new cache maintenance function, idcache_inv_all, to the table, andIan Lepore2014-02-241-0/+11
* Add identification and necessary type checks for Krait CPU cores. Krait CPU i...Ganbold Tsagaankhuu2013-12-201-2/+2
* Switch off explicit broadcasting of the TLB flush operations for PJ4B CPUZbigniew Bodek2013-10-281-1/+1
* Remove not working and deprecated PJ4Bv6 supportZbigniew Bodek2013-10-281-9/+0
* Replace generic ARM11 option with more specificOleksandr Tymoshenko2012-12-201-1/+17
* Don't define intr_disable and intr_restore as macros. The macrosMarcel Moolenaar2012-11-271-8/+24
* Add support for ARM11 cpufuncOleksandr Tymoshenko2012-08-261-0/+7
* Merging projects/armv6, part 1Oleksandr Tymoshenko2012-08-151-2/+101
* trim trailing whitespaceWarner Losh2012-06-131-4/+4
* Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug'sAlexander Motin2010-09-181-0/+1
* Add support for FA626TE.Kevin Lo2010-05-041-6/+6
* Add support for Cavium Econa CNS11XX ARM boards. These boards wereRui Paulo2010-01-041-0/+23
* Fix confusing naming of Marvell ARM CPU specific routines.Rafal Jaworowski2009-01-091-11/+11
* Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.Rafal Jaworowski2008-10-131-0/+12
* Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. NotWarner Losh2007-10-181-3/+55
* Add a new set of functions to handle L2 cache. Make them no-op for everyOlivier Houchard2007-07-271-9/+20
* Remove __PKevin Lo2007-03-211-12/+12
* Identify the xscale 81342.Olivier Houchard2006-11-071-2/+24
* Finally bring it support for the i80219 XScale processor.Olivier Houchard2006-08-241-7/+10
* Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.Olivier Houchard2006-06-011-1/+1
* Bring in bits I forgot while importing write back support for arm9.Olivier Houchard2005-06-031-11/+13
* Start all license statements with /*-Warner Losh2005-01-051-1/+1
* Implement enough to be able to enter and leave DDB.Olivier Houchard2004-11-201-0/+1
* Use interrupts_disable() and interrupts_restore() as intr_disable() andOlivier Houchard2004-11-041-24/+6
* Nuke disable_intr() and enable_intr(), as it already exists elsewhere.Olivier Houchard2004-07-201-3/+1
* Implement a stub breakpoint().Olivier Houchard2004-07-121-0/+5
* Import FreeBSD/arm kernel bits.Olivier Houchard2004-05-141-0/+530