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-rw-r--r--sys/powerpc/aim/mmu_oea64.c1
-rw-r--r--sys/powerpc/aim/moea64_native.c3
2 files changed, 4 insertions, 0 deletions
diff --git a/sys/powerpc/aim/mmu_oea64.c b/sys/powerpc/aim/mmu_oea64.c
index cd791f851018..f7026d11f7a8 100644
--- a/sys/powerpc/aim/mmu_oea64.c
+++ b/sys/powerpc/aim/mmu_oea64.c
@@ -1114,6 +1114,7 @@ void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
&moea64_scratchpage_pvo[which]->pvo_pte.lpte,
moea64_scratchpage_pvo[which]->pvo_vpn);
+ isync();
}
void
diff --git a/sys/powerpc/aim/moea64_native.c b/sys/powerpc/aim/moea64_native.c
index a386b93b208e..18698366938c 100644
--- a/sys/powerpc/aim/moea64_native.c
+++ b/sys/powerpc/aim/moea64_native.c
@@ -292,6 +292,9 @@ moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
pvo_pt->pte_hi &= ~LPTE_VALID;
+ /* Finish all pending operations */
+ isync();
+
/*
* Force the reg & chg bits back into the PTEs.
*/