diff options
Diffstat (limited to 'sys/dev/cadence/if_cgem_hw.h')
| -rw-r--r-- | sys/dev/cadence/if_cgem_hw.h | 64 |
1 files changed, 63 insertions, 1 deletions
diff --git a/sys/dev/cadence/if_cgem_hw.h b/sys/dev/cadence/if_cgem_hw.h index fced73327d91..784b131a885e 100644 --- a/sys/dev/cadence/if_cgem_hw.h +++ b/sys/dev/cadence/if_cgem_hw.h @@ -35,6 +35,10 @@ * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 * and register definitions are in appendix B.18. + * + * Additional Reference: Zynq UltraScale+ Device Register Reference + * (UG1087 v1.7 Feb 8,2019): + * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html */ #ifndef _IF_CGEM_HW_H_ @@ -113,6 +117,7 @@ #define CGEM_USER_IO 0x00C /* User I/O */ #define CGEM_DMA_CFG 0x010 /* DMA Config */ +#define CGEM_DMA_CFG_ADDR_BUS_64 (1 << 30) #define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1 << 24) #define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16 #define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff << 16) @@ -290,6 +295,29 @@ #define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */ #define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */ +#define CGEM_DESIGN_CFG1 0x280 /* Design Configuration 1 */ +#define CGEM_DESIGN_CFG1_AXI_CACHE_WIDTH_MASK (0xfU << 28) +#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK (7 << 25) +#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_32 (1 << 25) +#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64 (2 << 25) +#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128 (4 << 25) +#define CGEM_DESIGN_CFG1_IRQ_READ_CLR (1 << 23) +#define CGEM_DESIGN_CFG1_NO_SNAPSHOT (1 << 22) +#define CGEM_DESIGN_CFG1_NO_STATS (1 << 21) +#define CGEM_DESIGN_CFG1_NO_SCAN_PINS (1 << 20) +#define CGEM_DESIGN_CFG1_USER_IN_WIDTH_MASK (0x1f << 15) +#define CGEM_DESIGN_CFG1_USER_OUT_WIDTH_MASK (0x1f << 10) +#define CGEM_DESIGN_CFG1_USER_IO (1 << 9) +#define CGEM_DESIGN_CFG1_APB_REV2 (1 << 8) +#define CGEM_DESIGN_CFG1_APB_REV1 (1 << 7) +#define CGEM_DESIGN_CFG1_EXT_FIFO_INTERFACE (1 << 6) +#define CGEM_DESIGN_CFG1_NO_INT_LOOPBACK (1 << 5) +#define CGEM_DESIGN_CFG1_INT_LOOPBACK (1 << 4) +#define CGEM_DESIGN_CFG1_TDC_50 (1 << 3) +#define CGEM_DESIGN_CFG1_RDC_50 (1 << 2) +#define CGEM_DESIGN_CFG1_SERDES (1 << 1) +#define CGEM_DESIGN_CFG1_NO_PCS (1 << 0) + #define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */ #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf << 26) @@ -330,7 +358,25 @@ #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf << 4) #define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf -/* Transmit Descriptors */ +#define CGEM_DESIGN_CFG6 0x294 /* Design Configuration 6 */ +#define CGEM_DESIGN_CFG6_ADDR_64B (1 << 23) /* 64-bit addr cap */ +#define CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK 0xfffe +#define CGEM_DESIGN_CFG6_DMA_PRIO_Q(n) (1 << (n)) + +#define CGEM_TX_QN_BAR(n) (0x440 + ((n) - 1) * 4) +#define CGEM_RX_QN_BAR(n) (0x480 + ((n) - 1) * 4) + +#define CGEM_TX_QBAR_HI 0x4C8 +#define CGEM_RX_QBAR_HI 0x4D4 + +/* + * Transmit Descriptors: two or four 32-bit words: + * word0: address + * word1: length and control + * word2: address upper 32-bits (64-bit mode) + * word3: unused (64-bit mode) + */ + struct cgem_tx_desc { uint32_t addr; uint32_t ctl; @@ -350,8 +396,20 @@ struct cgem_tx_desc { #define CGEM_TXDESC_NO_CRC_APPENDED (1 << 16) #define CGEM_TXDESC_LAST_BUF (1 << 15) /* last in frame */ #define CGEM_TXDESC_LENGTH_MASK 0x3fff +#ifdef CGEM64 + uint32_t addrhi; + uint32_t unused; +#endif }; +/* + * Receive Descriptors: two or four 32-bit words: + * word0: address | WRAP and OWN flags + * word1: length and control + * word2: address upper 32 bits (64-bit mode) + * word3: unused + */ + struct cgem_rx_desc { uint32_t addr; #define CGEM_RXDESC_WRAP (1 << 1) /* goes in addr! */ @@ -379,6 +437,10 @@ struct cgem_rx_desc { #define CGEM_RXDESC_SOF (1 << 14) /* start of frame */ #define CGEM_RXDESC_BAD_FCS (1 << 13) #define CGEM_RXDESC_LENGTH_MASK 0x1fff +#ifdef CGEM64 + uint32_t addrhi; + uint32_t unused; +#endif }; #endif /* _IF_CGEM_HW_H_ */ |