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-rw-r--r--sys/arm64/apple/apple_pinctrl.c469
-rw-r--r--sys/arm64/apple/exynos_uart.c568
-rw-r--r--sys/arm64/apple/exynos_uart.h136
-rw-r--r--sys/arm64/arm64/gicv3_its.c2
-rw-r--r--sys/arm64/arm64/locore.S22
-rw-r--r--sys/arm64/arm64/pmap.c3
-rw-r--r--sys/arm64/arm64/trap.c3
-rw-r--r--sys/arm64/include/pte.h3
-rw-r--r--sys/arm64/rockchip/rk_grf_gpio.c236
-rw-r--r--sys/arm64/vmm/vmm.c17
10 files changed, 1453 insertions, 6 deletions
diff --git a/sys/arm64/apple/apple_pinctrl.c b/sys/arm64/apple/apple_pinctrl.c
new file mode 100644
index 000000000000..ec2dd5907024
--- /dev/null
+++ b/sys/arm64/apple/apple_pinctrl.c
@@ -0,0 +1,469 @@
+/* $OpenBSD: aplpinctrl.c,v 1.4 2022/04/06 18:59:26 naddy Exp $ */
+/*
+ * Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
+ * Copyright (c) 2022 Kyle Evans <kevans@FreeBSD.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <machine/resource.h>
+
+#include <dev/gpio/gpiobusvar.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/fdt/fdt_pinctrl.h>
+
+#include "pic_if.h"
+#include "gpio_if.h"
+
+#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
+#define APPLE_FUNC(pinmux) ((pinmux) >> 16)
+
+#define GPIO_PIN(pin) ((pin) * 4)
+#define GPIO_PIN_GROUP_MASK (7 << 16)
+#define GPIO_PIN_INPUT_ENABLE (1 << 9)
+#define GPIO_PIN_FUNC_MASK (3 << 5)
+#define GPIO_PIN_FUNC_SHIFT 5
+#define GPIO_PIN_MODE_MASK (7 << 1)
+#define GPIO_PIN_MODE_INPUT (0 << 1)
+#define GPIO_PIN_MODE_OUTPUT (1 << 1)
+#define GPIO_PIN_MODE_IRQ_HI (2 << 1)
+#define GPIO_PIN_MODE_IRQ_LO (3 << 1)
+#define GPIO_PIN_MODE_IRQ_UP (4 << 1)
+#define GPIO_PIN_MODE_IRQ_DN (5 << 1)
+#define GPIO_PIN_MODE_IRQ_ANY (6 << 1)
+#define GPIO_PIN_MODE_IRQ_OFF (7 << 1)
+#define GPIO_PIN_DATA (1 << 0)
+#define GPIO_IRQ(grp, pin) (0x800 + (grp) * 64 + ((pin) >> 5) * 4)
+
+#define APPLE_PINCTRL_DEFAULT_CAPS \
+ (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
+
+#define HREAD4(sc, reg) \
+ bus_read_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg)
+#define HWRITE4(sc, reg, val) \
+ bus_write_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg, val)
+#define HSET4(sc, reg, bits) \
+ HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
+#define HCLR4(sc, reg, bits) \
+ HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
+
+struct apple_pinctrl_irqsrc {
+ struct intr_irqsrc isrc;
+ int irq;
+ int type;
+};
+
+enum {
+ APPLE_PINCTRL_MEMRES = 0,
+ APPLE_PINCTRL_IRQRES,
+ APPLE_PINCTRL_NRES,
+};
+
+struct apple_pinctrl_softc {
+ device_t sc_dev;
+ device_t sc_busdev;
+ struct mtx sc_mtx;
+ int sc_ngpios;
+
+ void *sc_intrhand;
+ struct resource *sc_res[APPLE_PINCTRL_NRES];
+ struct apple_pinctrl_irqsrc *sc_irqs;
+};
+
+#define APPLE_PINCTRL_LOCK(sc) mtx_lock_spin(&(sc)->sc_mtx)
+#define APPLE_PINCTRL_UNLOCK(sc) mtx_unlock_spin(&(sc)->sc_mtx)
+#define APPLE_PINCTRL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
+
+static struct ofw_compat_data compat_data[] = {
+ {"apple,pinctrl", 1},
+ {NULL, 0},
+};
+
+static struct resource_spec apple_pinctrl_res_spec[] = {
+ { SYS_RES_MEMORY, 0, RF_ACTIVE },
+ { SYS_RES_IRQ, 0, RF_ACTIVE },
+ { -1, 0, 0 },
+};
+
+static int apple_pinctrl_probe(device_t dev);
+static int apple_pinctrl_attach(device_t dev);
+static int apple_pinctrl_detach(device_t dev);
+
+static int apple_pinctrl_configure(device_t, phandle_t);
+static phandle_t apple_pinctrl_get_node(device_t, device_t);
+
+static int
+apple_pinctrl_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Apple Pinmux Controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+apple_pinctrl_attach(device_t dev)
+{
+ pcell_t gpio_ranges[4];
+ phandle_t node;
+ struct apple_pinctrl_softc *sc;
+ int error;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ node = ofw_bus_get_node(dev);
+
+ if (bus_alloc_resources(dev, apple_pinctrl_res_spec, sc->sc_res) != 0) {
+ device_printf(dev, "cannot allocate device resources\n");
+ return (ENXIO);
+ }
+
+ mtx_init(&sc->sc_mtx, "aapl gpio", "gpio", MTX_SPIN);
+
+ error = OF_getencprop(node, "gpio-ranges", gpio_ranges,
+ sizeof(gpio_ranges));
+ if (error == -1) {
+ device_printf(dev, "failed to get gpio-ranges\n");
+ goto error;
+ }
+
+ sc->sc_ngpios = gpio_ranges[3];
+ if (sc->sc_ngpios == 0) {
+ device_printf(dev, "no GPIOs\n");
+ goto error;
+ }
+
+ sc->sc_busdev = gpiobus_attach_bus(dev);
+ if (sc->sc_busdev == NULL) {
+ device_printf(dev, "failed to attach gpiobus\n");
+ goto error;
+ }
+
+ fdt_pinctrl_register(dev, "pinmux");
+ fdt_pinctrl_configure_tree(dev);
+
+ if (!OF_hasprop(node, "interrupt-controller"))
+ return (0);
+
+ sc->sc_irqs = mallocarray(sc->sc_ngpios,
+ sizeof(*sc->sc_irqs), M_DEVBUF, M_ZERO | M_WAITOK);
+ intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
+
+ return (0);
+error:
+ mtx_destroy(&sc->sc_mtx);
+ bus_release_resources(dev, apple_pinctrl_res_spec, sc->sc_res);
+ return (ENXIO);
+}
+
+static int
+apple_pinctrl_detach(device_t dev)
+{
+
+ return (EBUSY);
+}
+
+static void
+apple_pinctrl_pin_configure(struct apple_pinctrl_softc *sc, uint32_t pin,
+ uint32_t flags)
+{
+ uint32_t reg;
+
+ APPLE_PINCTRL_LOCK_ASSERT(sc);
+
+ MPASS(pin < sc->sc_ngpios);
+
+ reg = HREAD4(sc, GPIO_PIN(pin));
+ reg &= ~GPIO_PIN_FUNC_MASK;
+ reg &= ~GPIO_PIN_MODE_MASK;
+
+ if ((flags & GPIO_PIN_PRESET_LOW) != 0)
+ reg &= ~GPIO_PIN_DATA;
+ else if ((flags & GPIO_PIN_PRESET_HIGH) != 0)
+ reg |= GPIO_PIN_DATA;
+
+ if ((flags & GPIO_PIN_INPUT) != 0)
+ reg |= GPIO_PIN_MODE_INPUT;
+ else if ((flags & GPIO_PIN_OUTPUT) != 0)
+ reg |= GPIO_PIN_MODE_OUTPUT;
+
+ HWRITE4(sc, GPIO_PIN(pin), reg);
+}
+
+static device_t
+apple_pinctrl_get_bus(device_t dev)
+{
+ struct apple_pinctrl_softc *sc;
+
+ sc = device_get_softc(dev);
+ return (sc->sc_busdev);
+}
+
+static int
+apple_pinctrl_pin_max(device_t dev, int *maxpin)
+{
+ struct apple_pinctrl_softc *sc;
+
+ sc = device_get_softc(dev);
+ *maxpin = sc->sc_ngpios - 1;
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ struct apple_pinctrl_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ snprintf(name, GPIOMAXNAME - 1, "gpio%c%d",
+ device_get_unit(dev) + 'a', pin);
+
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
+{
+ struct apple_pinctrl_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ *flags = 0;
+
+ APPLE_PINCTRL_LOCK(sc);
+
+ reg = HREAD4(sc, GPIO_PIN(pin));
+ if ((reg & GPIO_PIN_MODE_INPUT) != 0)
+ *flags |= GPIO_PIN_INPUT;
+ else if ((reg & GPIO_PIN_MODE_OUTPUT) != 0)
+ *flags |= GPIO_PIN_OUTPUT;
+
+ APPLE_PINCTRL_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+
+ *caps = APPLE_PINCTRL_DEFAULT_CAPS;
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
+{
+ struct apple_pinctrl_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ APPLE_PINCTRL_LOCK(sc);
+ apple_pinctrl_pin_configure(sc, pin, flags);
+ APPLE_PINCTRL_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_get(device_t dev, uint32_t pin, unsigned int *val)
+{
+ struct apple_pinctrl_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ APPLE_PINCTRL_LOCK(sc);
+ reg = HREAD4(sc, GPIO_PIN(pin));
+ *val = !!(reg & GPIO_PIN_DATA);
+ APPLE_PINCTRL_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+apple_pinctrl_pin_set(device_t dev, uint32_t pin, unsigned int value)
+{
+ struct apple_pinctrl_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ APPLE_PINCTRL_LOCK(sc);
+ if (value)
+ HSET4(sc, GPIO_PIN(pin), GPIO_PIN_DATA);
+ else
+ HCLR4(sc, GPIO_PIN(pin), GPIO_PIN_DATA);
+ device_printf(sc->sc_dev, "set pin %d to %x\n",
+ pin, HREAD4(sc, GPIO_PIN(pin)));
+ APPLE_PINCTRL_UNLOCK(sc);
+ return (0);
+}
+
+
+static int
+apple_pinctrl_pin_toggle(device_t dev, uint32_t pin)
+{
+ struct apple_pinctrl_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ APPLE_PINCTRL_LOCK(sc);
+ reg = HREAD4(sc, GPIO_PIN(pin));
+ if ((reg & GPIO_PIN_DATA) == 0)
+ reg |= GPIO_PIN_DATA;
+ else
+ reg &= ~GPIO_PIN_DATA;
+ HWRITE4(sc, GPIO_PIN(pin), reg);
+ APPLE_PINCTRL_UNLOCK(sc);
+ return (0);
+}
+
+
+static int
+apple_pinctrl_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
+ uint32_t *pin_flags)
+{
+ struct apple_pinctrl_softc *sc;
+ uint32_t pin;
+
+ sc = device_get_softc(dev);
+ if (first_pin >= sc->sc_ngpios)
+ return (EINVAL);
+
+ /*
+ * The configuration for a bank of pins is scattered among several
+ * registers; we cannot g'tee to simultaneously change the state of all
+ * the pins in the flags array. So just loop through the array
+ * configuring each pin for now. If there was a strong need, it might
+ * be possible to support some limited simultaneous config, such as
+ * adjacent groups of 8 pins that line up the same as the config regs.
+ */
+ APPLE_PINCTRL_LOCK(sc);
+ for (pin = first_pin; pin < num_pins; ++pin) {
+ if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
+ apple_pinctrl_pin_configure(sc, pin, pin_flags[pin]);
+ }
+ APPLE_PINCTRL_UNLOCK(sc);
+
+ return (0);
+}
+
+static phandle_t
+apple_pinctrl_get_node(device_t dev, device_t bus)
+{
+
+ /* GPIO bus */
+ return (ofw_bus_get_node(dev));
+}
+
+static int
+apple_pinctrl_configure(device_t dev, phandle_t cfgxref)
+{
+ struct apple_pinctrl_softc *sc;
+ pcell_t *pinmux;
+ phandle_t node;
+ ssize_t len;
+ uint32_t reg;
+ uint16_t pin, func;
+ int i;
+
+ sc = device_get_softc(dev);
+ node = OF_node_from_xref(cfgxref);
+
+ len = OF_getencprop_alloc(node, "pinmux", (void **)&pinmux);
+ if (len <= 0)
+ return (-1);
+
+ APPLE_PINCTRL_LOCK(sc);
+ for (i = 0; i < len / sizeof(pcell_t); i++) {
+ pin = APPLE_PIN(pinmux[i]);
+ func = APPLE_FUNC(pinmux[i]);
+ reg = HREAD4(sc, GPIO_PIN(pin));
+ reg &= ~GPIO_PIN_FUNC_MASK;
+ reg |= (func << GPIO_PIN_FUNC_SHIFT) & GPIO_PIN_FUNC_MASK;
+ HWRITE4(sc, GPIO_PIN(pin), reg);
+ }
+ APPLE_PINCTRL_UNLOCK(sc);
+
+ OF_prop_free(pinmux);
+ return 0;
+}
+
+static device_method_t apple_pinctrl_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, apple_pinctrl_probe),
+ DEVMETHOD(device_attach, apple_pinctrl_attach),
+ DEVMETHOD(device_detach, apple_pinctrl_detach),
+
+ /* GPIO protocol */
+ DEVMETHOD(gpio_get_bus, apple_pinctrl_get_bus),
+ DEVMETHOD(gpio_pin_max, apple_pinctrl_pin_max),
+ DEVMETHOD(gpio_pin_getname, apple_pinctrl_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, apple_pinctrl_pin_getflags),
+ DEVMETHOD(gpio_pin_getcaps, apple_pinctrl_pin_getcaps),
+ DEVMETHOD(gpio_pin_setflags, apple_pinctrl_pin_setflags),
+ DEVMETHOD(gpio_pin_get, apple_pinctrl_pin_get),
+ DEVMETHOD(gpio_pin_set, apple_pinctrl_pin_set),
+ DEVMETHOD(gpio_pin_toggle, apple_pinctrl_pin_toggle),
+ DEVMETHOD(gpio_pin_config_32, apple_pinctrl_pin_config_32),
+
+ /* ofw_bus interface */
+ DEVMETHOD(ofw_bus_get_node, apple_pinctrl_get_node),
+
+ /* fdt_pinctrl interface */
+ DEVMETHOD(fdt_pinctrl_configure, apple_pinctrl_configure),
+
+ DEVMETHOD_END
+};
+
+static driver_t apple_pinctrl_driver = {
+ "gpio",
+ apple_pinctrl_methods,
+ sizeof(struct apple_pinctrl_softc),
+};
+
+EARLY_DRIVER_MODULE(apple_pinctrl, simplebus, apple_pinctrl_driver,
+ 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
diff --git a/sys/arm64/apple/exynos_uart.c b/sys/arm64/apple/exynos_uart.c
new file mode 100644
index 000000000000..2767c338b918
--- /dev/null
+++ b/sys/arm64/apple/exynos_uart.c
@@ -0,0 +1,568 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2003 Marcel Moolenaar
+ * Copyright (c) 2007-2009 Andrew Turner
+ * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/cons.h>
+#include <sys/rman.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_cpu_fdt.h>
+#include <dev/uart/uart_bus.h>
+
+#include <arm64/apple/exynos_uart.h>
+
+#include "uart_if.h"
+
+struct exynos_uart_cfg;
+
+#define DEF_CLK 100000000
+
+static int sscomspeed(long, long);
+static int exynos4210_uart_param(struct uart_bas *, int, int, int, int);
+
+/*
+ * Low-level UART interface.
+ */
+static int exynos4210_probe(struct uart_bas *bas);
+static void exynos4210_init_common(struct exynos_uart_cfg *cfg,
+ struct uart_bas *bas, int, int, int, int);
+static void exynos4210_init(struct uart_bas *bas, int, int, int, int);
+static void exynos4210_s5l_init(struct uart_bas *bas, int, int, int, int);
+static void exynos4210_term(struct uart_bas *bas);
+static void exynos4210_putc(struct uart_bas *bas, int);
+static int exynos4210_rxready(struct uart_bas *bas);
+static int exynos4210_getc(struct uart_bas *bas, struct mtx *mtx);
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static struct uart_ops uart_exynos4210_ops;
+static struct uart_ops uart_s5l_ops;
+static kobj_method_t exynos4210_methods[];
+static kobj_method_t s5l_methods[];
+static struct ofw_compat_data compat_data[];
+
+enum exynos_uart_type {
+ EXUART_4210,
+ EXUART_S5L,
+};
+
+struct exynos_uart_cfg {
+ enum exynos_uart_type cfg_type;
+ uint64_t cfg_uart_full_mask;
+};
+
+struct exynos_uart_class {
+ struct uart_class base;
+ struct exynos_uart_cfg cfg;
+};
+
+static struct exynos_uart_class uart_ex4210_class = {
+ .base = {
+ "exynos4210 class",
+ exynos4210_methods,
+ 1,
+ .uc_ops = &uart_exynos4210_ops,
+ .uc_range = 8,
+ .uc_rclk = 0,
+ .uc_rshift = 0
+ },
+ .cfg = {
+ .cfg_type = EXUART_4210,
+ .cfg_uart_full_mask = UFSTAT_TXFULL,
+ },
+};
+
+
+static struct exynos_uart_class uart_s5l_class = {
+ .base = {
+ "s5l class",
+ s5l_methods,
+ 1,
+ .uc_ops = &uart_s5l_ops,
+ .uc_range = 8,
+ .uc_rclk = 0,
+ .uc_rshift = 0
+ },
+ .cfg = {
+ .cfg_type = EXUART_S5L,
+ .cfg_uart_full_mask = UFSTAT_S5L_TXFULL,
+ },
+};
+
+static int
+sscomspeed(long speed, long frequency)
+{
+ int x;
+
+ if (speed <= 0 || frequency <= 0)
+ return (-1);
+ x = (frequency / 16) / speed;
+ return (x-1);
+}
+
+static int
+exynos4210_uart_param(struct uart_bas *bas, int baudrate, int databits,
+ int stopbits, int parity)
+{
+ int brd, ulcon;
+
+ ulcon = 0;
+
+ switch(databits) {
+ case 5:
+ ulcon |= ULCON_LENGTH_5;
+ break;
+ case 6:
+ ulcon |= ULCON_LENGTH_6;
+ break;
+ case 7:
+ ulcon |= ULCON_LENGTH_7;
+ break;
+ case 8:
+ ulcon |= ULCON_LENGTH_8;
+ break;
+ default:
+ return (EINVAL);
+ }
+
+ switch (parity) {
+ case UART_PARITY_NONE:
+ ulcon |= ULCON_PARITY_NONE;
+ break;
+ case UART_PARITY_ODD:
+ ulcon |= ULCON_PARITY_ODD;
+ break;
+ case UART_PARITY_EVEN:
+ ulcon |= ULCON_PARITY_EVEN;
+ break;
+ case UART_PARITY_MARK:
+ case UART_PARITY_SPACE:
+ default:
+ return (EINVAL);
+ }
+
+ if (stopbits == 2)
+ ulcon |= ULCON_STOP;
+
+ uart_setreg(bas, SSCOM_ULCON, ulcon);
+
+ /* baudrate may be negative, in which case we just leave it alone. */
+ if (baudrate > 0) {
+ brd = sscomspeed(baudrate, bas->rclk);
+ uart_setreg(bas, SSCOM_UBRDIV, brd);
+ }
+
+ return (0);
+}
+
+static struct uart_ops uart_exynos4210_ops = {
+ .probe = exynos4210_probe,
+ .init = exynos4210_init,
+ .term = exynos4210_term,
+ .putc = exynos4210_putc,
+ .rxready = exynos4210_rxready,
+ .getc = exynos4210_getc,
+};
+
+static struct uart_ops uart_s5l_ops = {
+ .probe = exynos4210_probe,
+ .init = exynos4210_s5l_init,
+ .term = exynos4210_term,
+ .putc = exynos4210_putc,
+ .rxready = exynos4210_rxready,
+ .getc = exynos4210_getc,
+};
+
+static int
+exynos4210_probe(struct uart_bas *bas)
+{
+
+ return (0);
+}
+
+static void
+exynos4210_init_common(struct exynos_uart_cfg *cfg, struct uart_bas *bas,
+ int baudrate, int databits, int stopbits, int parity)
+{
+
+ if (bas->rclk == 0)
+ bas->rclk = DEF_CLK;
+
+ KASSERT(bas->rclk != 0, ("exynos4210_init: Invalid rclk"));
+
+ bas->driver1 = cfg;
+
+ /* Clear interrupts */
+ if (cfg->cfg_type == EXUART_S5L) {
+ uart_setreg(bas, SSCOM_UTRSTAT, 0);
+ } else {
+ uart_setreg(bas, SSCOM_UCON, 0);
+ uart_setreg(bas, SSCOM_UFCON,
+ UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 |
+ UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET |
+ UFCON_FIFO_ENABLE);
+ }
+
+ exynos4210_uart_param(bas, baudrate, databits, stopbits, parity);
+
+ /* Enable UART. */
+ if (cfg->cfg_type == EXUART_S5L) {
+ uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |
+ UCON_TOINT | UCON_S5L_RXTHRESH | UCON_S5L_RX_TIMEOUT |
+ UCON_S5L_TXTHRESH);
+ } else {
+ uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) |
+ UCON_TXMODE_INT | UCON_RXMODE_INT | UCON_TOINT);
+ uart_setreg(bas, SSCOM_UMCON, UMCON_RTS);
+ }
+}
+
+static void
+exynos4210_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+
+ return (exynos4210_init_common(&uart_ex4210_class.cfg, bas, baudrate,
+ databits, stopbits, parity));
+}
+
+static void
+exynos4210_s5l_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+
+ return (exynos4210_init_common(&uart_s5l_class.cfg, bas, baudrate,
+ databits, stopbits, parity));
+}
+
+static void
+exynos4210_term(struct uart_bas *bas)
+{
+ /* XXX */
+}
+
+static void
+exynos4210_putc(struct uart_bas *bas, int c)
+{
+ struct exynos_uart_cfg *cfg;
+
+ cfg = bas->driver1;
+
+ while ((bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT) &
+ cfg->cfg_uart_full_mask) != 0)
+ continue;
+
+ uart_setreg(bas, SSCOM_UTXH, c);
+ uart_barrier(bas);
+}
+
+static int
+exynos4210_rxready_impl(struct uart_bas *bas, bool intr)
+{
+ struct exynos_uart_cfg *cfg;
+ int ufstat, utrstat;
+
+ cfg = bas->driver1;
+ if (!intr || cfg->cfg_type != EXUART_S5L) {
+ utrstat = bus_space_read_4(bas->bst, bas->bsh, SSCOM_UTRSTAT);
+
+ if ((utrstat & UTRSTAT_RXREADY) != 0)
+ return (1);
+ if (cfg->cfg_type != EXUART_S5L)
+ return (0);
+ }
+
+ ufstat = bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT);
+
+ return ((ufstat & (UFSTAT_RXCOUNT | UFSTAT_RXFULL)) != 0);
+}
+
+static int
+exynos4210_rxready(struct uart_bas *bas)
+{
+
+ return (exynos4210_rxready_impl(bas, false));
+}
+
+static int
+exynos4210_getc(struct uart_bas *bas, struct mtx *mtx)
+{
+
+ while (!exynos4210_rxready(bas)) {
+ continue;
+ }
+
+ return (uart_getreg(bas, SSCOM_URXH));
+}
+
+static int exynos4210_bus_probe(struct uart_softc *sc);
+static int exynos4210_bus_attach(struct uart_softc *sc);
+static int exynos4210_bus_flush(struct uart_softc *, int);
+static int exynos4210_bus_getsig(struct uart_softc *);
+static int exynos4210_bus_ioctl(struct uart_softc *, int, intptr_t);
+static int exynos4210_bus_ipend(struct uart_softc *);
+static int s5l_bus_ipend(struct uart_softc *);
+static int exynos4210_bus_param(struct uart_softc *, int, int, int, int);
+static int exynos4210_bus_receive(struct uart_softc *);
+static int exynos4210_bus_setsig(struct uart_softc *, int);
+static int exynos4210_bus_transmit(struct uart_softc *);
+
+static kobj_method_t exynos4210_methods[] = {
+ KOBJMETHOD(uart_probe, exynos4210_bus_probe),
+ KOBJMETHOD(uart_attach, exynos4210_bus_attach),
+ KOBJMETHOD(uart_flush, exynos4210_bus_flush),
+ KOBJMETHOD(uart_getsig, exynos4210_bus_getsig),
+ KOBJMETHOD(uart_ioctl, exynos4210_bus_ioctl),
+ KOBJMETHOD(uart_ipend, exynos4210_bus_ipend),
+ KOBJMETHOD(uart_param, exynos4210_bus_param),
+ KOBJMETHOD(uart_receive, exynos4210_bus_receive),
+ KOBJMETHOD(uart_setsig, exynos4210_bus_setsig),
+ KOBJMETHOD(uart_transmit, exynos4210_bus_transmit),
+ {0, 0 }
+};
+
+static kobj_method_t s5l_methods[] = {
+ KOBJMETHOD(uart_probe, exynos4210_bus_probe),
+ KOBJMETHOD(uart_attach, exynos4210_bus_attach),
+ KOBJMETHOD(uart_flush, exynos4210_bus_flush),
+ KOBJMETHOD(uart_getsig, exynos4210_bus_getsig),
+ KOBJMETHOD(uart_ioctl, exynos4210_bus_ioctl),
+ KOBJMETHOD(uart_ipend, s5l_bus_ipend),
+ KOBJMETHOD(uart_param, exynos4210_bus_param),
+ KOBJMETHOD(uart_receive, exynos4210_bus_receive),
+ KOBJMETHOD(uart_setsig, exynos4210_bus_setsig),
+ KOBJMETHOD(uart_transmit, exynos4210_bus_transmit),
+ {0, 0 }
+};
+
+int
+exynos4210_bus_probe(struct uart_softc *sc)
+{
+
+ sc->sc_txfifosz = 16;
+ sc->sc_rxfifosz = 16;
+
+ return (0);
+}
+
+static int
+exynos4210_bus_attach(struct uart_softc *sc)
+{
+ struct exynos_uart_class *class;
+ struct exynos_uart_cfg *cfg;
+
+ sc->sc_hwiflow = 0;
+ sc->sc_hwoflow = 0;
+
+ class = (struct exynos_uart_class *)ofw_bus_search_compatible(sc->sc_dev,
+ compat_data)->ocd_data;
+ MPASS(class != NULL);
+
+ cfg = &class->cfg;
+ MPASS(sc->sc_sysdev == NULL || cfg == sc->sc_sysdev->bas.driver1);
+ sc->sc_bas.driver1 = cfg;
+
+ return (0);
+}
+
+static int
+exynos4210_bus_transmit(struct uart_softc *sc)
+{
+ struct exynos_uart_cfg *cfg;
+ int i;
+ int reg;
+
+ cfg = sc->sc_bas.driver1;
+ uart_lock(sc->sc_hwmtx);
+
+ /* tx fifo has room, fire away. */
+ for (i = 0; i < sc->sc_txdatasz; i++) {
+ uart_setreg(&sc->sc_bas, SSCOM_UTXH, sc->sc_txbuf[i]);
+ uart_barrier(&sc->sc_bas);
+ }
+
+ if (cfg->cfg_type == EXUART_S5L) {
+ sc->sc_txbusy = 1;
+ } else {
+ /* unmask TX interrupt */
+ reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,
+ SSCOM_UINTM);
+ reg &= ~(1 << 2);
+ bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM,
+ reg);
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+
+ return (0);
+}
+
+static int
+exynos4210_bus_setsig(struct uart_softc *sc, int sig)
+{
+
+ return (0);
+}
+
+static int
+exynos4210_bus_receive(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+
+ while (exynos4210_rxready_impl(bas, true)) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
+ break;
+ }
+
+ uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+
+ return (0);
+}
+
+static int
+exynos4210_bus_param(struct uart_softc *sc, int baudrate, int databits,
+ int stopbits, int parity)
+{
+ int error;
+
+ if (sc->sc_bas.rclk == 0)
+ sc->sc_bas.rclk = DEF_CLK;
+
+ KASSERT(sc->sc_bas.rclk != 0, ("exynos4210_init: Invalid rclk"));
+
+ uart_lock(sc->sc_hwmtx);
+ error = exynos4210_uart_param(&sc->sc_bas, baudrate, databits, stopbits,
+ parity);
+ uart_unlock(sc->sc_hwmtx);
+
+ return (error);
+}
+
+static int
+s5l_bus_ipend(struct uart_softc *sc)
+{
+ int ipend;
+ uint32_t uerstat, utrstat;
+
+ ipend = 0;
+ uart_lock(sc->sc_hwmtx);
+ utrstat = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,
+ SSCOM_UTRSTAT);
+
+ if (utrstat & (UTRSTAT_S5L_RXTHRESH | UTRSTAT_S5L_RX_TIMEOUT))
+ ipend |= SER_INT_RXREADY;
+
+ if (utrstat & UTRSTAT_S5L_TXTHRESH)
+ ipend |= SER_INT_TXIDLE;
+
+ uerstat = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,
+ SSCOM_UERSTAT);
+ if ((uerstat & UERSTAT_BREAK) != 0)
+ ipend |= SER_INT_BREAK;
+
+ bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UTRSTAT,
+ utrstat);
+ uart_unlock(sc->sc_hwmtx);
+
+ return (ipend);
+}
+
+static int
+exynos4210_bus_ipend(struct uart_softc *sc)
+{
+ uint32_t ints;
+ int reg;
+ int ipend;
+
+ uart_lock(sc->sc_hwmtx);
+ ints = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP);
+ bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP, ints);
+
+ ipend = 0;
+ if ((ints & UINTP_TXEMPTY) != 0) {
+ if (sc->sc_txbusy != 0)
+ ipend |= SER_INT_TXIDLE;
+
+ /* mask TX interrupt */
+ reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,
+ SSCOM_UINTM);
+ reg |= UINTM_TXINTR;
+ bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh,
+ SSCOM_UINTM, reg);
+ }
+
+ if ((ints & UINTP_RXREADY) != 0) {
+ ipend |= SER_INT_RXREADY;
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+ return (ipend);
+}
+
+static int
+exynos4210_bus_flush(struct uart_softc *sc, int what)
+{
+
+ return (0);
+}
+
+static int
+exynos4210_bus_getsig(struct uart_softc *sc)
+{
+
+ return (0);
+}
+
+static int
+exynos4210_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
+{
+
+ return (EINVAL);
+}
+
+static struct ofw_compat_data compat_data[] = {
+ {"apple,s5l-uart", (uintptr_t)&uart_s5l_class.base},
+ {"samsung,exynos4210-uart", (uintptr_t)&uart_ex4210_class.base},
+ {NULL, (uintptr_t)NULL},
+};
+UART_FDT_CLASS_AND_DEVICE(compat_data);
diff --git a/sys/arm64/apple/exynos_uart.h b/sys/arm64/apple/exynos_uart.h
new file mode 100644
index 000000000000..6c817252a69a
--- /dev/null
+++ b/sys/arm64/apple/exynos_uart.h
@@ -0,0 +1,136 @@
+/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */
+
+/*-
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2002, 2003 Fujitsu Component Limited
+ * Copyright (c) 2002, 2003 Genetec Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of The Fujitsu Component Limited nor the name of
+ * Genetec corporation may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
+ * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
+ * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* s3c2410-specific registers */
+#define UMCON_AFC (1 << 4) /* auto flow control */
+#define UMSTAT_DCTS (1 << 2) /* CTS change */
+#define ULCON_IR (1 << 6)
+#define ULCON_PARITY_SHIFT 3
+
+/*
+ * Exynos-specific
+ *
+ * UFSTAT_TXFULL register differs between Exynos and others.
+ * Others have UFSTAT_TXFULL (1 << 9)
+ */
+#define UFSTAT_TXFULL (1 << 24)
+#define UFSTAT_S5L_TXFULL (1 << 9)
+
+#define SSCOM_UINTM 0x038
+#define UINTM_TXINTR (1 << 2)
+#define SSCOM_UINTP 0x030
+#define UINTP_RXREADY (1 << 0)
+#define UINTP_TXEMPTY (1 << 2)
+
+/* common for s3c2800 and s3c24x0 */
+#define SSCOM_ULCON 0x00 /* UART line control */
+#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT)
+#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT)
+#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT)
+#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT)
+#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT)
+#define ULCON_STOP (1 << 2)
+#define ULCON_LENGTH_5 0
+#define ULCON_LENGTH_6 1
+#define ULCON_LENGTH_7 2
+#define ULCON_LENGTH_8 3
+#define SSCOM_UCON 0x04 /* UART control */
+#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */
+#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE
+#define UCON_TXINT_TYPE_PULSE 0
+#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */
+#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE
+#define UCON_RXINT_TYPE_PULSE 0
+#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */
+#define UCON_ERRINT (1 << 6) /* receive error interrupt */
+#define UCON_LOOP (1 << 5) /* loopback */
+#define UCON_SBREAK (1 << 4) /* send break */
+#define UCON_TXMODE_DISABLE (0 << 2)
+#define UCON_TXMODE_INT (1 << 2)
+#define UCON_TXMODE_DMA (2 << 2)
+#define UCON_TXMODE_MASK (3 << 2)
+#define UCON_RXMODE_DISABLE (0 << 0)
+#define UCON_RXMODE_INT (1 << 0)
+#define UCON_RXMODE_DMA (2 << 0)
+#define UCON_RXMODE_MASK (3 << 0)
+#define UCON_S5L_RX_TIMEOUT (0x1 << 9)
+#define UCON_S5L_RXTHRESH (0x1 << 12)
+#define UCON_S5L_TXTHRESH (0x1 << 13)
+#define SSCOM_UFCON 0x08 /* FIFO control */
+#define UFCON_TXTRIGGER_0 (0 << 6)
+#define UFCON_TXTRIGGER_4 (1 << 6)
+#define UFCON_TXTRIGGER_8 (2 << 6)
+#define UFCON_TXTRIGGER_16 (3 << 6)
+#define UFCON_RXTRIGGER_4 (0 << 4)
+#define UFCON_RXTRIGGER_8 (1 << 4)
+#define UFCON_RXTRIGGER_12 (2 << 4)
+#define UFCON_RXTRIGGER_16 (3 << 4)
+#define UFCON_TXFIFO_RESET (1 << 2)
+#define UFCON_RXFIFO_RESET (1 << 1)
+#define UFCON_FIFO_ENABLE (1 << 0)
+#define SSCOM_UMCON 0x0c /* MODEM control */
+#define UMCON_RTS (1 << 0) /* Request to send */
+#define SSCOM_UTRSTAT 0x10 /* Status register */
+#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2)
+#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */
+#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */
+#define UTRSTAT_S5L_RXTHRESH (0x1 << 4)
+#define UTRSTAT_S5L_TXTHRESH (0x1 << 5)
+#define UTRSTAT_S5L_RX_TIMEOUT (0x1 << 9)
+#define SSCOM_UERSTAT 0x14 /* Error status register */
+#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */
+#define UERSTAT_FRAME (1 << 2) /* Frame error */
+#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */
+#define UERSTAT_OVERRUN (1 << 0) /* Overrun */
+#define UERSTAT_ALL_ERRORS \
+ (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
+#define SSCOM_UFSTAT 0x18 /* Fifo status register */
+#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */
+#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */
+#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT)
+#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
+#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT)
+#define SSCOM_UMSTAT 0x1c /* Modem status register */
+#define UMSTAT_CTS (1 << 0) /* Clear to send */
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+#define SSCOM_UTXH 0x20 /* Transmit data register */
+#define SSCOM_URXH 0x24 /* Receive data register */
+#else
+#define SSCOM_UTXH 0x23 /* Transmit data register */
+#define SSCOM_URXH 0x27 /* Receive data register */
+#endif
+#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */
+#define SSCOM_SIZE 0x2c
diff --git a/sys/arm64/arm64/gicv3_its.c b/sys/arm64/arm64/gicv3_its.c
index 77d1936d8c95..546a225abf09 100644
--- a/sys/arm64/arm64/gicv3_its.c
+++ b/sys/arm64/arm64/gicv3_its.c
@@ -801,7 +801,7 @@ its_init_cpu_lpi(device_t dev, struct gicv3_its_softc *sc)
/* Make sure changes are observable my the GIC */
dsb(sy);
- size = (flsl(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1);
+ size = ilog2_long(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1;
xbaser = vtophys(sc->sc_conf_base) |
(GICR_PROPBASER_SHARE_IS << GICR_PROPBASER_SHARE_SHIFT) |
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 88193b6c93f7..9cf23fcf13a1 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -87,6 +87,7 @@ ENTRY(_start)
* x26 = Kernel L1 table
* x24 = TTBR1 table
* x22 = PTE shareability attributes
+ * x21 = BTI guarded page attribute if supported
*/
/* Enable the mmu */
@@ -136,9 +137,13 @@ virtdone:
str x27, [x0, #BP_KERN_TTBR0]
str x23, [x0, #BP_BOOT_EL]
- /* Set this before it's used in kasan_init_early */
+ /* Set these before they are used in kasan_init_early */
adrp x1, pmap_sh_attr
str x22, [x1, :lo12:pmap_sh_attr]
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+ adrp x1, pmap_gp_attr
+ str x21, [x1, :lo12:pmap_gp_attr]
+#endif
#ifdef KASAN
/* Save bootparams */
@@ -487,6 +492,17 @@ LENTRY(create_pagetables)
cmp x6, x27
b.lo 1b
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+ /*
+ * Check if the CPU supports BTI
+ */
+ mrs x6, id_aa64pfr1_el1 /* Read the ID register */
+ and x6, x6, ID_AA64PFR1_BT_MASK /* Mask the field we need */
+ cmp x6, xzr /* Check it's non-zero */
+ cset x6, ne /* x6 is set if non-zero */
+ lsl x21, x6, ATTR_S1_GP_SHIFT /* Shift to the correct bit */
+#endif
+
/*
* Find the shareability attribute we should use. If FEAT_LPA2 is
* enabled then the shareability field is moved from the page table
@@ -785,7 +801,7 @@ LENTRY(build_l2_block_pagetable)
orr x12, x12, #(ATTR_AF)
orr x12, x12, #(ATTR_S1_UXN)
#ifdef __ARM_FEATURE_BTI_DEFAULT
- orr x12, x12, #(ATTR_S1_GP)
+ orr x12, x12, x21
#endif
/* Set the shareability attribute */
orr x12, x12, x22
@@ -863,7 +879,7 @@ LENTRY(build_l3_page_pagetable)
orr x12, x12, #(ATTR_AF)
orr x12, x12, #(ATTR_S1_UXN)
#ifdef __ARM_FEATURE_BTI_DEFAULT
- orr x12, x12, #(ATTR_S1_GP)
+ orr x12, x12, x21
#endif
/* Set the shareability attribute */
orr x12, x12, x22
diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
index 5a3dbbf00203..14ef7dd0169c 100644
--- a/sys/arm64/arm64/pmap.c
+++ b/sys/arm64/arm64/pmap.c
@@ -182,7 +182,8 @@
#define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
#ifdef __ARM_FEATURE_BTI_DEFAULT
-#define ATTR_KERN_GP ATTR_S1_GP
+pt_entry_t __read_mostly pmap_gp_attr;
+#define ATTR_KERN_GP pmap_gp_attr
#else
#define ATTR_KERN_GP 0
#endif
diff --git a/sys/arm64/arm64/trap.c b/sys/arm64/arm64/trap.c
index d612905b77c8..fdcc38cd9a31 100644
--- a/sys/arm64/arm64/trap.c
+++ b/sys/arm64/arm64/trap.c
@@ -85,6 +85,9 @@ static void print_registers(struct trapframe *frame);
int (*dtrace_invop_jump_addr)(struct trapframe *);
+u_long cnt_efirt_faults;
+int print_efirt_faults;
+
typedef void (abort_handler)(struct thread *, struct trapframe *, uint64_t,
uint64_t, int);
diff --git a/sys/arm64/include/pte.h b/sys/arm64/include/pte.h
index ae6a8694f6c4..464d8c941c56 100644
--- a/sys/arm64/include/pte.h
+++ b/sys/arm64/include/pte.h
@@ -73,7 +73,8 @@ typedef uint64_t pt_entry_t; /* page table entry */
#define ATTR_CONTIGUOUS (1UL << 52)
#define ATTR_DBM (1UL << 51)
-#define ATTR_S1_GP (1UL << 50)
+#define ATTR_S1_GP_SHIFT 50
+#define ATTR_S1_GP (1UL << ATTR_S1_GP_SHIFT)
/*
* Largest possible output address field for a level 3 page. Block
diff --git a/sys/arm64/rockchip/rk_grf_gpio.c b/sys/arm64/rockchip/rk_grf_gpio.c
new file mode 100644
index 000000000000..6818bd85bb95
--- /dev/null
+++ b/sys/arm64/rockchip/rk_grf_gpio.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2025 Stephen Hurd <shurd@FreeBSD.org>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/gpio/gpiobusvar.h>
+#include <dev/syscon/syscon.h>
+
+#include "syscon_if.h"
+
+#define GRF_SOC_CON10 0x0428
+#define SOC_CON10_GPIOMUT (1 << 1)
+#define SOC_CON10_GPIOMUT_MASK ((1 << 1) << 16)
+#define SOC_CON10_GPIOMUT_EN (1 << 0)
+#define SOC_CON10_GPIOMUT_EN_MASK ((1 << 0) << 16)
+
+struct rk_grf_gpio_softc {
+ device_t sc_dev;
+ device_t sc_busdev;
+ struct syscon *sc_grf;
+ bool active_high;
+};
+
+static struct ofw_compat_data compat_data[] = {
+ {"rockchip,rk3328-grf-gpio", 1},
+ {NULL, 0}
+};
+
+static device_t
+rk_grf_gpio_get_bus(device_t dev)
+{
+ struct rk_grf_gpio_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ return (sc->sc_busdev);
+}
+
+static int
+rk_grf_gpio_pin_max(device_t dev, int *maxpin)
+{
+ *maxpin = 1;
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ if (pin)
+ return (EINVAL);
+
+ snprintf(name, GPIOMAXNAME, "GPIO_MUTE");
+
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
+{
+ if (pin)
+ return (EINVAL);
+ *flags = GPIO_PIN_OUTPUT;
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
+{
+ if (pin)
+ return (EINVAL);
+ if (flags != GPIO_PIN_OUTPUT)
+ return (EINVAL);
+
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+ if (pin)
+ return (EINVAL);
+
+ *caps = GPIO_PIN_OUTPUT;
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
+{
+ struct rk_grf_gpio_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+
+ if (pin)
+ return (EINVAL);
+
+ reg = SYSCON_READ_4(sc->sc_grf, GRF_SOC_CON10);
+ if (reg & SOC_CON10_GPIOMUT)
+ *val = 1;
+ else
+ *val = 0;
+
+ return (0);
+}
+
+static int
+rk_grf_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
+{
+ struct rk_grf_gpio_softc *sc;
+ uint32_t val;
+
+ sc = device_get_softc(dev);
+
+ if (pin)
+ return (EINVAL);
+
+ val = SOC_CON10_GPIOMUT_MASK;
+ if (value)
+ val |= SOC_CON10_GPIOMUT;
+ SYSCON_WRITE_4(sc->sc_grf, GRF_SOC_CON10, val);
+
+ return (0);
+}
+
+static int
+rk_grf_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
+ pcell_t *gpios, uint32_t *pin, uint32_t *flags)
+{
+ if (gpios[0])
+ return (EINVAL);
+
+ /* The gpios are mapped as <pin flags> */
+ *pin = 0;
+ /* TODO: The only valid flags are active low or active high */
+ *flags = GPIO_PIN_OUTPUT;
+ return (0);
+}
+
+static int
+rk_grf_gpio_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "RockChip General Register File GPIO (GPIO_MUTE)");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+rk_grf_gpio_attach(device_t dev)
+{
+ struct rk_grf_gpio_softc *sc;
+ phandle_t parent_node, node;
+ device_t pdev;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ node = ofw_bus_get_node(sc->sc_dev);
+ if (!OF_hasprop(node, "gpio-controller"))
+ return (ENXIO);
+ pdev = device_get_parent(dev);
+ parent_node = ofw_bus_get_node(pdev);
+ if (syscon_get_by_ofw_node(dev, parent_node, &sc->sc_grf) != 0) {
+ device_printf(dev, "cannot get parent syscon handle\n");
+ return (ENXIO);
+ }
+
+ sc->sc_busdev = gpiobus_attach_bus(dev);
+ if (sc->sc_busdev == NULL) {
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+static int
+rk_grf_gpio_detach(device_t dev)
+{
+ struct rk_grf_gpio_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ if (sc->sc_busdev)
+ gpiobus_detach_bus(dev);
+
+ return(0);
+}
+
+static device_method_t rk_grf_gpio_methods[] = {
+ DEVMETHOD(device_probe, rk_grf_gpio_probe),
+ DEVMETHOD(device_attach, rk_grf_gpio_attach),
+ DEVMETHOD(device_detach, rk_grf_gpio_detach),
+
+ /* GPIO protocol */
+ DEVMETHOD(gpio_get_bus, rk_grf_gpio_get_bus),
+ DEVMETHOD(gpio_pin_max, rk_grf_gpio_pin_max),
+ DEVMETHOD(gpio_pin_getname, rk_grf_gpio_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, rk_grf_gpio_pin_getflags),
+ DEVMETHOD(gpio_pin_setflags, rk_grf_gpio_pin_setflags),
+ DEVMETHOD(gpio_pin_getcaps, rk_grf_gpio_pin_getcaps),
+ DEVMETHOD(gpio_pin_get, rk_grf_gpio_pin_get),
+ DEVMETHOD(gpio_pin_set, rk_grf_gpio_pin_set),
+ DEVMETHOD(gpio_map_gpios, rk_grf_gpio_map_gpios),
+
+ DEVMETHOD_END
+};
+
+static driver_t rk_grf_gpio_driver = {
+ "gpio",
+ rk_grf_gpio_methods,
+ sizeof(struct rk_grf_gpio_softc),
+};
+
+/*
+ * GPIO driver is always a child of rk_grf driver and should be probed
+ * and attached within rk_grf function. Due to this, bus pass order
+ * must be same as bus pass order of rk_grf driver.
+ */
+EARLY_DRIVER_MODULE(rk_grf_gpio, simplebus, rk_grf_gpio_driver, 0, 0,
+ BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
diff --git a/sys/arm64/vmm/vmm.c b/sys/arm64/vmm/vmm.c
index ad82e6dbd432..f28643db99d2 100644
--- a/sys/arm64/vmm/vmm.c
+++ b/sys/arm64/vmm/vmm.c
@@ -311,6 +311,20 @@ vm_exitinfo(struct vcpu *vcpu)
}
static int
+vmm_unsupported_quirk(void)
+{
+ /*
+ * Known to not load on Ampere eMAG
+ * https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=285051
+ */
+ if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, CPU_IMPL_APM,
+ CPU_PART_EMAG8180, 0, 0))
+ return (ENXIO);
+
+ return (0);
+}
+
+static int
vmm_init(void)
{
int error;
@@ -339,6 +353,9 @@ vmm_handler(module_t mod, int what, void *arg)
switch (what) {
case MOD_LOAD:
+ error = vmm_unsupported_quirk();
+ if (error != 0)
+ break;
error = vmmdev_init();
if (error != 0)
break;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 22:55:49 +0000