diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86TargetTransformInfo.h')
| -rw-r--r-- | llvm/lib/Target/X86/X86TargetTransformInfo.h | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 69715072426f..bd3c3fb1bb2f 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -38,12 +38,12 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> { const FeatureBitset InlineFeatureIgnoreList = { // This indicates the CPU is 64 bit capable not that we are in 64-bit // mode. - X86::Feature64Bit, + X86::FeatureX86_64, // These features don't have any intrinsics or ABI effect. X86::FeatureNOPL, - X86::FeatureCMPXCHG16B, - X86::FeatureLAHFSAHF, + X86::FeatureCX16, + X86::FeatureLAHFSAHF64, // Some older targets can be setup to fold unaligned loads. X86::FeatureSSEUnalignedMem, @@ -68,6 +68,11 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> { X86::TuningMacroFusion, X86::TuningPadShortFunctions, X86::TuningPOPCNTFalseDeps, + X86::TuningMULCFalseDeps, + X86::TuningPERMFalseDeps, + X86::TuningRANGEFalseDeps, + X86::TuningGETMANTFalseDeps, + X86::TuningMULLQFalseDeps, X86::TuningSlow3OpsLEA, X86::TuningSlowDivide32, X86::TuningSlowDivide64, @@ -131,7 +136,8 @@ public: const Instruction *CxtI = nullptr); InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask, int Index, - VectorType *SubTp); + VectorType *SubTp, + ArrayRef<const Value *> Args = None); InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, @@ -219,13 +225,14 @@ public: InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); - bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, - TargetTransformInfo::LSRCost &C2); + bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, + const TargetTransformInfo::LSRCost &C2); bool canMacroFuseCmp(); bool isLegalMaskedLoad(Type *DataType, Align Alignment); bool isLegalMaskedStore(Type *DataType, Align Alignment); bool isLegalNTLoad(Type *DataType, Align Alignment); bool isLegalNTStore(Type *DataType, Align Alignment); + bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const; bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment); bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) { return forceScalarizeMaskedGather(VTy, Alignment); @@ -234,6 +241,8 @@ public: bool isLegalMaskedScatter(Type *DataType, Align Alignment); bool isLegalMaskedExpandLoad(Type *DataType); bool isLegalMaskedCompressStore(Type *DataType); + bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, + const SmallBitVector &OpcodeMask) const; bool hasDivRemOp(Type *DataType, bool IsSigned); bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); bool areInlineCompatible(const Function *Caller, |