diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedIceLake.td')
-rw-r--r-- | llvm/lib/Target/X86/X86SchedIceLake.td | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td index 9fd986e34181..b66db7e7e73a 100644 --- a/llvm/lib/Target/X86/X86SchedIceLake.td +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -923,12 +923,26 @@ def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { - let Latency = 3; + let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[ICXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", - "RCR(8|16|32|64)r(1|i)")>; +def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, + RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; + +def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { + let Latency = 5; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; + +def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { + let Latency = 6; + let NumMicroOps = 7; + let ResourceCycles = [2,3,2]; +} +def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { let Latency = 3; |