diff options
Diffstat (limited to 'llvm/lib/Target/VE/VERegisterInfo.td')
| -rw-r--r-- | llvm/lib/Target/VE/VERegisterInfo.td | 104 |
1 files changed, 77 insertions, 27 deletions
diff --git a/llvm/lib/Target/VE/VERegisterInfo.td b/llvm/lib/Target/VE/VERegisterInfo.td index 29708d35c730..70ff104b65b7 100644 --- a/llvm/lib/Target/VE/VERegisterInfo.td +++ b/llvm/lib/Target/VE/VERegisterInfo.td @@ -26,13 +26,33 @@ class VEMiscReg<bits<6> enc, string n>: Register<n> { let Namespace = "VE"; } +class VEVecReg<bits<8> enc, string n, list<Register> subregs = [], + list<string> altNames = [], list<Register> aliases = []> + : Register<n, altNames> { + let HWEncoding{15-8} = 0; + let HWEncoding{7-0} = enc; + let Namespace = "VE"; + let SubRegs = subregs; + let Aliases = aliases; +} + +class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [], + list<string> altNames = [], list<Register> aliases = []> + : Register<n, altNames> { + let HWEncoding{15-4} = 0; + let HWEncoding{3-0} = enc; + let Namespace = "VE"; + let SubRegs = subregs; + let Aliases = aliases; +} + let Namespace = "VE" in { - def sub_i8 : SubRegIndex<8, 56>; // Low 8 bit (56..63) - def sub_i16 : SubRegIndex<16, 48>; // Low 16 bit (48..63) def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) def sub_even : SubRegIndex<64>; // High 64 bit (0..63) def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127) + def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255) + def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511) def AsmName : RegAltNameIndex; } @@ -66,26 +86,23 @@ def MISC : RegisterClass<"VE", [i64], 64, def IC : VEMiscReg<62, "ic">; //----------------------------------------------------------------------------- -// Gneric Registers +// Vector Length Register //----------------------------------------------------------------------------- -let RegAltNameIndices = [AsmName] in { +def VL : VEMiscReg<63, "vl">; -// Generic integer registers - 8 bits wide -foreach I = 0-63 in - def SB#I : VEReg<I, "sb"#I, [], ["s"#I]>, DwarfRegNum<[I]>; +// Register classes. +def VLS : RegisterClass<"VE", [i32], 64, (add VL)>; -// Generic integer registers - 16 bits wide -let SubRegIndices = [sub_i8] in -foreach I = 0-63 in - def SH#I : VEReg<I, "sh"#I, [!cast<VEReg>("SB"#I)], ["s"#I]>, - DwarfRegNum<[I]>; +//----------------------------------------------------------------------------- +// Generic Registers +//----------------------------------------------------------------------------- + +let RegAltNameIndices = [AsmName] in { // Generic integer registers - 32 bits wide -let SubRegIndices = [sub_i16] in foreach I = 0-63 in - def SW#I : VEReg<I, "sw"#I, [!cast<VEReg>("SH"#I)], ["s"#I]>, - DwarfRegNum<[I]>; + def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>; // Generic floating point registers - 32 bits wide // NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation @@ -95,10 +112,21 @@ foreach I = 0-63 in DwarfRegNum<[I]>; // Generic integer registers - 64 bits wide -let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in -foreach I = 0-63 in - def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)], - ["s"#I]>, DwarfRegNum<[I]>; +let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in { + // Several registers have specific names, so add them to one of aliases. + def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>; + def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>; + def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>; + def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>; + def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>; + def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>; + def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>; + + // Other generic registers. + foreach I = { 0-7, 12-13, 17-63 } in + def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)], + ["s"#I]>, DwarfRegNum<[I]>; +} // Aliases of the S* registers used to hold 128-bit for values (long doubles). // Following foreach represents something like: @@ -112,20 +140,31 @@ foreach I = 0-31 in !cast<VEReg>("SX"#!add(!shl(I,1),1))], ["s"#!shl(I,1)]>; +// Vector registers - 64 bits wide 256 elements +foreach I = 0-63 in + def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>; + +// Vector Index Register +def VIX : VEVecReg<255, "vix", [], ["vix"]>; + +// Vector mask registers - 256 bits wide +foreach I = 0-15 in + def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>; + +// Aliases of VMs to use as a pair of two VM for packed instructions +let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in +foreach I = 0-7 in + def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I, + [!cast<VEMaskReg>("VM"#!shl(I,1)), + !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))], + ["vm"#!shl(I,1)]>; + } // RegAltNameIndices = [AsmName] // Register classes. // // The register order is defined in terms of the preferred // allocation order. -def I8 : RegisterClass<"VE", [i8], 8, - (add (sequence "SB%u", 0, 7), - (sequence "SB%u", 34, 63), - (sequence "SB%u", 8, 33))>; -def I16 : RegisterClass<"VE", [i16], 16, - (add (sequence "SH%u", 0, 7), - (sequence "SH%u", 34, 63), - (sequence "SH%u", 8, 33))>; def I32 : RegisterClass<"VE", [i32], 32, (add (sequence "SW%u", 0, 7), (sequence "SW%u", 34, 63), @@ -142,3 +181,14 @@ def F128 : RegisterClass<"VE", [f128], 128, (add (sequence "Q%u", 0, 3), (sequence "Q%u", 17, 31), (sequence "Q%u", 4, 16))>; + +def V64 : RegisterClass<"VE", + [v256f64, // default type for vector registers + v512i32, v512f32, + v256i64, v256i32, v256f32, /* v256f64, */], 64, + (add (sequence "V%u", 0, 63), + VIX)>; + +// vm0 is reserved for always true +def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>; +def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>; |