diff options
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.h')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index 46c1b73d512f..8b98ad3dceea 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -96,16 +96,29 @@ public: bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const; + /// Predicate to determine if an instruction can go in a load delay slot. + bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, + const MachineInstr &LoadMI) const; + /// Predicate to determine if an instruction has a forbidden slot. bool HasForbiddenSlot(const MachineInstr &MI) const; /// Predicate to determine if an instruction has an FPU delay slot. bool HasFPUDelaySlot(const MachineInstr &MI) const; + /// Predicate to determine if an instruction has a load delay slot. + bool HasLoadDelaySlot(const MachineInstr &MI) const; + /// Insert nop instruction when hazard condition is found void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override; + /// Insert an ISA appropriate `nop`. + // FIXME: Add support for MIPS16e. + MachineInstrBuilder insertNop(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + DebugLoc DL) const; + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). |