diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 98c8133282a2..e0e4ffd90e0e 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1058,15 +1058,15 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr, MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) { // This case occurs only for VLD1-lane/dup and VST1-lane instructions. // The maximum alignment is equal to the memory size being referenced. - unsigned MMOAlign = MemN->getAlignment(); + llvm::Align MMOAlign = MemN->getAlign(); unsigned MemSize = MemN->getMemoryVT().getSizeInBits() / 8; - if (MMOAlign >= MemSize && MemSize > 1) + if (MMOAlign.value() >= MemSize && MemSize > 1) Alignment = MemSize; } else { // All other uses of addrmode6 are for intrinsics. For now just record // the raw alignment value; it will be refined later based on the legal // alignment operands for the intrinsic. - Alignment = MemN->getAlignment(); + Alignment = MemN->getAlign().value(); } Align = CurDAG->getTargetConstant(Alignment, SDLoc(N), MVT::i32); @@ -3464,40 +3464,39 @@ bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) { return false; } -/// Target-specific DAG combining for ISD::XOR. +/// Target-specific DAG combining for ISD::SUB. /// Target-independent combining lowers SELECT_CC nodes of the form /// select_cc setg[ge] X, 0, X, -X /// select_cc setgt X, -1, X, -X /// select_cc setl[te] X, 0, -X, X /// select_cc setlt X, 1, -X, X /// which represent Integer ABS into: -/// Y = sra (X, size(X)-1); xor (add (X, Y), Y) +/// Y = sra (X, size(X)-1); sub (xor (X, Y), Y) /// ARM instruction selection detects the latter and matches it to /// ARM::ABS or ARM::t2ABS machine node. bool ARMDAGToDAGISel::tryABSOp(SDNode *N){ - SDValue XORSrc0 = N->getOperand(0); - SDValue XORSrc1 = N->getOperand(1); + SDValue SUBSrc0 = N->getOperand(0); + SDValue SUBSrc1 = N->getOperand(1); EVT VT = N->getValueType(0); if (Subtarget->isThumb1Only()) return false; - if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA) + if (SUBSrc0.getOpcode() != ISD::XOR || SUBSrc1.getOpcode() != ISD::SRA) return false; - SDValue ADDSrc0 = XORSrc0.getOperand(0); - SDValue ADDSrc1 = XORSrc0.getOperand(1); - SDValue SRASrc0 = XORSrc1.getOperand(0); - SDValue SRASrc1 = XORSrc1.getOperand(1); + SDValue XORSrc0 = SUBSrc0.getOperand(0); + SDValue XORSrc1 = SUBSrc0.getOperand(1); + SDValue SRASrc0 = SUBSrc1.getOperand(0); + SDValue SRASrc1 = SUBSrc1.getOperand(1); ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1); EVT XType = SRASrc0.getValueType(); unsigned Size = XType.getSizeInBits() - 1; - if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && - XType.isInteger() && SRAConstant != nullptr && - Size == SRAConstant->getZExtValue()) { + if (XORSrc1 == SUBSrc1 && XORSrc0 == SRASrc0 && XType.isInteger() && + SRAConstant != nullptr && Size == SRAConstant->getZExtValue()) { unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; - CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0); + CurDAG->SelectNodeTo(N, Opcode, VT, XORSrc0); return true; } @@ -3673,8 +3672,8 @@ void ARMDAGToDAGISel::Select(SDNode *N) { if (tryInlineAsm(N)) return; break; - case ISD::XOR: - // Select special operations if XOR node forms integer ABS pattern + case ISD::SUB: + // Select special operations if SUB node forms integer ABS pattern if (tryABSOp(N)) return; // Other cases are autogenerated. |