diff options
Diffstat (limited to 'lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json')
| -rw-r--r-- | lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json | 173 |
1 files changed, 0 insertions, 173 deletions
diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json b/lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json deleted file mode 100644 index ad989207e8f8..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereex/virtual-memory.json +++ /dev/null @@ -1,173 +0,0 @@ -[ - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_LOAD_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.PDE_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_MISSES.PDE_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE." - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_MISSES.STLB_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_MISSES.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" - }, - { - "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" - }, - { - "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_FLUSH", - "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" - }, - { - "PEBS": "1", - "EventCode": "0xC8", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_STORE_RETIRED.DTLB_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" - } -]
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