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-rw-r--r--lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/other.json287
1 files changed, 0 insertions, 287 deletions
diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/other.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/other.json
deleted file mode 100644
index 85133d6a5ce0..000000000000
--- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-sp/other.json
+++ /dev/null
@@ -1,287 +0,0 @@
-[
- {
- "EventCode": "0xE8",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Early Branch Prediciton Unit clears"
- },
- {
- "EventCode": "0xE8",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Late Branch Prediction Unit clears"
- },
- {
- "EventCode": "0xE5",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Branch prediction unit missed call or return"
- },
- {
- "EventCode": "0xD5",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "ES_REG_RENAMES",
- "SampleAfterValue": "2000000",
- "BriefDescription": "ES segment renames"
- },
- {
- "EventCode": "0x6C",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "IO_TRANSACTIONS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "I/O transactions"
- },
- {
- "EventCode": "0x80",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "L1I.CYCLES_STALLED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch stall cycles"
- },
- {
- "EventCode": "0x80",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "L1I.HITS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch hits"
- },
- {
- "EventCode": "0x80",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "L1I.MISSES",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch misses"
- },
- {
- "EventCode": "0x80",
- "Counter": "0,1,2,3",
- "UMask": "0x3",
- "EventName": "L1I.READS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1I Instruction fetches"
- },
- {
- "EventCode": "0x82",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "LARGE_ITLB.HIT",
- "SampleAfterValue": "200000",
- "BriefDescription": "Large ITLB hit"
- },
- {
- "EventCode": "0x3",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "LOAD_BLOCK.OVERLAP_STORE",
- "SampleAfterValue": "200000",
- "BriefDescription": "Loads that partially overlap an earlier store"
- },
- {
- "EventCode": "0x13",
- "Counter": "0,1,2,3",
- "UMask": "0x7",
- "EventName": "LOAD_DISPATCH.ANY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "All loads dispatched"
- },
- {
- "EventCode": "0x13",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "LOAD_DISPATCH.MOB",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from the MOB"
- },
- {
- "EventCode": "0x13",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "LOAD_DISPATCH.RS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched that bypass the MOB"
- },
- {
- "EventCode": "0x13",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "LOAD_DISPATCH.RS_DELAYED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from stage 305"
- },
- {
- "EventCode": "0x7",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "PARTIAL_ADDRESS_ALIAS",
- "SampleAfterValue": "200000",
- "BriefDescription": "False dependencies due to partial address aliasing"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0xf",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "All RAT stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Flag stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Partial register stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "BriefDescription": "ROB read port stalls cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x8",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Scoreboard stall cycles"
- },
- {
- "EventCode": "0x4",
- "Counter": "0,1,2,3",
- "UMask": "0x7",
- "EventName": "SB_DRAIN.ANY",
- "SampleAfterValue": "200000",
- "BriefDescription": "All Store buffer stall cycles"
- },
- {
- "EventCode": "0xD4",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "SEG_RENAME_STALLS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Segment rename stall cycles"
- },
- {
- "EventCode": "0xB8",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "SNOOP_RESPONSE.HIT",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HIT to snoop"
- },
- {
- "EventCode": "0xB8",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "SNOOP_RESPONSE.HITE",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITE to snoop"
- },
- {
- "EventCode": "0xB8",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "SNOOP_RESPONSE.HITM",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITM to snoop"
- },
- {
- "EventCode": "0xB4",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "SNOOPQ_REQUESTS.CODE",
- "SampleAfterValue": "100000",
- "BriefDescription": "Snoop code requests"
- },
- {
- "EventCode": "0xB4",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "SNOOPQ_REQUESTS.DATA",
- "SampleAfterValue": "100000",
- "BriefDescription": "Snoop data requests"
- },
- {
- "EventCode": "0xB4",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
- "SampleAfterValue": "100000",
- "BriefDescription": "Snoop invalidate requests"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x4",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop code requests"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x4",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop code requests queued",
- "CounterMask": "1"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x1",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop data requests"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x1",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop data requests queued",
- "CounterMask": "1"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x2",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop invalidate requests"
- },
- {
- "EventCode": "0xB3",
- "UMask": "0x2",
- "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop invalidate requests queued",
- "CounterMask": "1"
- },
- {
- "EventCode": "0xF6",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "SQ_FULL_STALL_CYCLES",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Super Queue full stall cycles"
- }
-] \ No newline at end of file
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-23 16:28:54 +0000