diff options
Diffstat (limited to 'lib/libpmcstat/pmu-events/arch/x86/westmereep-dp')
7 files changed, 0 insertions, 5189 deletions
diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/cache.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/cache.json deleted file mode 100644 index 6e61ae20d01a..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/cache.json +++ /dev/null @@ -1,2817 +0,0 @@ -[ - { - "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "CACHE_LOCK_CYCLES.L1D", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" - }, - { - "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CACHE_LOCK_CYCLES.L1D_L2", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" - }, - { - "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "L1D.M_EVICT", - "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" - }, - { - "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "L1D.M_REPL", - "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" - }, - { - "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D.M_SNOOP_EVICT", - "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" - }, - { - "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "L1D.REPL", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" - }, - { - "EventCode": "0x52", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" - }, - { - "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "L1D_PREFETCH.MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" - }, - { - "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "L1D_PREFETCH.REQUESTS", - "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" - }, - { - "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "L1D_PREFETCH.TRIGGERS", - "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1D_WB_L2.E_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D_WB_L2.I_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", - "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_WB_L2.S_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_DATA_RQSTS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" - }, - { - "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_LINES_OUT.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", - "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", - "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.LD_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_RQSTS.LD_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.LOADS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xaa", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANSACTIONS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANSACTIONS.FILL", - "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANSACTIONS.IFETCH", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANSACTIONS.L1D_WB", - "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANSACTIONS.LOAD", - "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANSACTIONS.PREFETCH", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANSACTIONS.RFO", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANSACTIONS.WB", - "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_WRITE.LOCK.E_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xe0", - "EventName": "L2_WRITE.LOCK.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_WRITE.LOCK.I_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", - "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_WRITE.LOCK.S_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "L2_WRITE.RFO.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_WRITE.RFO.I_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", - "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_WRITE.RFO.S_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OFFCORE_REQUESTS.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ANY.READ", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OFFCORE_REQUESTS.ANY.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", - "MSRIndex": "0x3F6", - "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f44", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff44", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x50ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7fff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xffff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - 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"Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f10", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff10", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f40", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff40", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f20", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff20", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f70", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff70", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/floating-point.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/floating-point.json deleted file mode 100644 index 7d2f71a9dee3..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/floating-point.json +++ /dev/null @@ -1,229 +0,0 @@ -[ - { - "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_ASSIST.ALL", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.INPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.OUTPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_COMP_OPS_EXE.MMX", - "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_COMP_OPS_EXE.SSE_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations executed" - }, - { - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "FP_MMX_TRANS.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transitions" - }, - { - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_MMX_TRANS.TO_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instructions" - }, - { - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_MMX_TRANS.TO_MMX", - "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instructions" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SIMD_INT_128.PACK", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "SIMD_INT_128.PACKED_ARITH", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SIMD_INT_128.PACKED_LOGICAL", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_INT_128.PACKED_MPY", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_INT_128.PACKED_SHIFT", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "SIMD_INT_128.SHUFFLE_MOVE", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" - }, - { - "EventCode": "0x12", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "SIMD_INT_128.UNPACK", - "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SIMD_INT_64.PACK", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "SIMD_INT_64.PACKED_ARITH", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SIMD_INT_64.PACKED_LOGICAL", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_INT_64.PACKED_MPY", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_INT_64.PACKED_SHIFT", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "SIMD_INT_64.SHUFFLE_MOVE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" - }, - { - "EventCode": "0xFD", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "SIMD_INT_64.UNPACK", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/frontend.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/frontend.json deleted file mode 100644 index e5e21e03444d..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/frontend.json +++ /dev/null @@ -1,26 +0,0 @@ -[ - { - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACRO_INSTS.DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" - }, - { - "EventCode": "0xA6", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACRO_INSTS.FUSIONS_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" - }, - { - "EventCode": "0x19", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TWO_UOP_INSTS_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/memory.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/memory.json deleted file mode 100644 index 6e0829b7617f..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/memory.json +++ /dev/null @@ -1,758 +0,0 @@ -[ - { - "EventCode": "0x5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORE", - "SampleAfterValue": "200000", - "BriefDescription": "Misaligned store references" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf811", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2011", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf844", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2044", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x30ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf8ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x40ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20ff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf822", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf808", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf877", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3033", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf833", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4033", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2033", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3003", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf803", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf801", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf804", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf802", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf880", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3050", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf850", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4050", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2050", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf810", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf840", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf820", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf870", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2070", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/other.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/other.json deleted file mode 100644 index 85133d6a5ce0..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/other.json +++ /dev/null @@ -1,287 +0,0 @@ -[ - { - "EventCode": "0xE8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BPU_CLEARS.EARLY", - "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" - }, - { - "EventCode": "0xE8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BPU_CLEARS.LATE", - "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" - }, - { - "EventCode": "0xE5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BPU_MISSED_CALL_RET", - "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" - }, - { - "EventCode": "0xD5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ES_REG_RENAMES", - "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" - }, - { - "EventCode": "0x6C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IO_TRANSACTIONS", - "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1I.CYCLES_STALLED", - "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1I.HITS", - "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1I.MISSES", - "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L1I.READS", - "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" - }, - { - "EventCode": "0x82", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LARGE_ITLB.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" - }, - { - "EventCode": "0x3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_BLOCK.OVERLAP_STORE", - "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" - }, - { - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "LOAD_DISPATCH.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" - }, - { - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "LOAD_DISPATCH.MOB", - "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" - }, - { - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_DISPATCH.RS", - "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" - }, - { - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_DISPATCH.RS_DELAYED", - "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" - }, - { - "EventCode": "0x7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PARTIAL_ADDRESS_ALIAS", - "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address aliasing" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RAT_STALLS.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RAT_STALLS.FLAGS", - "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RAT_STALLS.REGISTERS", - "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RAT_STALLS.ROB_READ_PORT", - "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RAT_STALLS.SCOREBOARD", - "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" - }, - { - "EventCode": "0x4", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "SB_DRAIN.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" - }, - { - "EventCode": "0xD4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SEG_RENAME_STALLS", - "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { - "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOPQ_REQUESTS.CODE", - "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" - }, - { - "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOPQ_REQUESTS.DATA", - "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" - }, - { - "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOPQ_REQUESTS.INVALIDATE", - "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" - }, - { - "EventCode": "0xB3", - "UMask": "0x4", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" - }, - { - "EventCode": "0xB3", - "UMask": "0x4", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" - }, - { - "EventCode": "0xB3", - "UMask": "0x1", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" - }, - { - "EventCode": "0xB3", - "UMask": "0x1", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" - }, - { - "EventCode": "0xB3", - "UMask": "0x2", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" - }, - { - "EventCode": "0xB3", - "UMask": "0x2", - "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" - }, - { - "EventCode": "0xF6", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SQ_FULL_STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/pipeline.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/pipeline.json deleted file mode 100644 index f130510f7616..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/pipeline.json +++ /dev/null @@ -1,899 +0,0 @@ -[ - { - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.CYCLES_DIV_BUSY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" - }, - { - "EventCode": "0x14", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.DIV", - "SampleAfterValue": "2000000", - "BriefDescription": "Divide Operations executed", - "CounterMask": "1", - "EdgeDetect": "1" - }, - { - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ARITH.MUL", - "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" - }, - { - "EventCode": "0xE6", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BACLEAR.BAD_TARGET", - "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" - }, - { - "EventCode": "0xE6", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BACLEAR.CLEAR", - "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " - }, - { - "EventCode": "0xA7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BACLEAR_FORCE_IQ", - "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" - }, - { - "EventCode": "0xE0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x7f", - "EventName": "BR_INST_EXEC.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_EXEC.COND", - "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_EXEC.DIRECT", - "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "BR_INST_EXEC.NEAR_CALLS", - "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "BR_INST_EXEC.NON_CALLS", - "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_EXEC.RETURN_NEAR", - "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_EXEC.TAKEN", - "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event)" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x7f", - "EventName": "BR_MISP_EXEC.ANY", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_EXEC.COND", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_EXEC.DIRECT", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "BR_MISP_EXEC.NEAR_CALLS", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "BR_MISP_EXEC.NON_CALLS", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_MISP_EXEC.RETURN_NEAR", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_MISP_EXEC.TAKEN", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Event)" - }, - { - "EventCode": "0x0", - "Counter": "Fixed counter 3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_P", - "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" - }, - { - "EventCode": "0x0", - "Counter": "Fixed counter 2", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed counter)" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmable counter)" - }, - { - "EventCode": "0x3C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Total CPU cycles", - "CounterMask": "2" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "ILD_STALL.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ILD_STALL.MRU", - "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "ILD_STALL.REGEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" - }, - { - "EventCode": "0x18", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_DECODED.DEC0", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder 0" - }, - { - "EventCode": "0x1E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instruction queue" - }, - { - "EventCode": "0x17", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." - }, - { - "EventCode": "0x0", - "Counter": "Fixed counter 1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" - }, - { - "PEBS": "1", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "INST_RETIRED.MMX", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "1", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Event)" - }, - { - "EventCode": "0x4C", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE", - "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software prefetches" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.ACTIVE", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" - }, - { - "EventCode": "0xA8", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.INACTIVE", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" - }, - { - "EventCode": "0x20", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD_OVERFLOW", - "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction queue" - }, - { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", - "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" - }, - { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEM_ORDER", - "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" - }, - { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RESOURCE_STALLS.FPCW", - "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.LOAD", - "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RESOURCE_STALLS.MXCSR", - "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RESOURCE_STALLS.OTHER", - "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB_FULL", - "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS_FULL", - "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.STORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" - }, - { - "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" - }, - { - "EventCode": "0xDB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DECODED.ESP_FOLDING", - "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" - }, - { - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DECODED.ESP_SYNC", - "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" - }, - { - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" - }, - { - "EventCode": "0xD1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DECODED.STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on any port (core count)", - "CounterMask": "1", - "EdgeDetect": "1" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on ports 0-4 (core count)", - "CounterMask": "1", - "EdgeDetect": "1" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on any port (core count)", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.PORT0", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.PORT1", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT234_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT3_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT4_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED.PORT5", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" - }, - { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" - }, - { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" - }, - { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" - }, - { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_ISSUED.FUSED", - "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" - }, - { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_RETIRED.MACRO_FUSED", - "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", - "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - } -]
\ No newline at end of file diff --git a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/virtual-memory.json deleted file mode 100644 index 57b53562e2bd..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ /dev/null @@ -1,173 +0,0 @@ -[ - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_LOAD_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.PDE_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" - }, - { - "EventCode": "0x8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_MISSES.PDE_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses casued by low part of address" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_MISSES.STLB_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_MISSES.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" - }, - { - "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" - }, - { - "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_FLUSH", - "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" - }, - { - "PEBS": "1", - "EventCode": "0xC8", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xC", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_STORE_RETIRED.DTLB_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" - } -]
\ No newline at end of file |