diff options
Diffstat (limited to 'lib/Target/R600/AMDGPUInstrInfo.h')
| -rw-r--r-- | lib/Target/R600/AMDGPUInstrInfo.h | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h index d5041f558163..da9833d25a52 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.h +++ b/lib/Target/R600/AMDGPUInstrInfo.h @@ -13,10 +13,9 @@ // //===----------------------------------------------------------------------===// -#ifndef AMDGPUINSTRUCTIONINFO_H -#define AMDGPUINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H +#define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H -#include "AMDGPUInstrInfo.h" #include "AMDGPURegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include <map> @@ -41,8 +40,6 @@ class MachineInstrBuilder; class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { private: const AMDGPURegisterInfo RI; - bool getNextBranchInstr(MachineBasicBlock::iterator &iter, - MachineBasicBlock &MBB) const; virtual void anchor(); protected: const AMDGPUSubtarget &ST; @@ -74,11 +71,6 @@ public: LiveVariables *LV) const override; - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const = 0; - bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, @@ -101,6 +93,7 @@ protected: MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const override; +public: /// \returns the smallest register index that will be accessed by an indirect /// read or write or -1 if indirect addressing is not used by this program. int getIndirectIndexBegin(const MachineFunction &MF) const; @@ -109,7 +102,6 @@ protected: /// read or write or -1 if indirect addressing is not used by this program. int getIndirectIndexEnd(const MachineFunction &MF) const; -public: bool canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const override; bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, @@ -120,6 +112,9 @@ public: unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex = nullptr) const override; + + bool enableClusterLoads() const override; + bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override; @@ -196,4 +191,4 @@ namespace AMDGPU { #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) -#endif // AMDGPUINSTRINFO_H +#endif |