diff options
Diffstat (limited to 'lib/CodeGen/VirtRegMap.cpp')
-rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 62 |
1 files changed, 37 insertions, 25 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index f8aacdb8649d..64bb37a280a6 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// +//===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===// // // The LLVM Compiler Infrastructure // @@ -18,24 +18,32 @@ #include "llvm/CodeGen/VirtRegMap.h" #include "LiveDebugVariables.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveInterval.h" +#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/IR/Function.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/MC/LaneBitmask.h" +#include "llvm/Pass.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetSubtargetInfo.h" -#include <algorithm> +#include <cassert> +#include <iterator> +#include <utility> + using namespace llvm; #define DEBUG_TYPE "regalloc" @@ -132,8 +140,8 @@ void VirtRegMap::print(raw_ostream &OS, const Module*) const { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) { - OS << '[' << PrintReg(Reg, TRI) << " -> " - << PrintReg(Virt2PhysMap[Reg], TRI) << "] " + OS << '[' << printReg(Reg, TRI) << " -> " + << printReg(Virt2PhysMap[Reg], TRI) << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } @@ -141,7 +149,7 @@ void VirtRegMap::print(raw_ostream &OS, const Module*) const { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { - OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] + OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } @@ -164,9 +172,9 @@ LLVM_DUMP_METHOD void VirtRegMap::dump() const { // according to LiveIntervals. // namespace { + class VirtRegRewriter : public MachineFunctionPass { MachineFunction *MF; - const TargetMachine *TM; const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; MachineRegisterInfo *MRI; @@ -184,18 +192,23 @@ class VirtRegRewriter : public MachineFunctionPass { public: static char ID; + VirtRegRewriter() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction&) override; + MachineFunctionProperties getSetProperties() const override { return MachineFunctionProperties().set( MachineFunctionProperties::Property::NoVRegs); } }; + } // end anonymous namespace +char VirtRegRewriter::ID = 0; + char &llvm::VirtRegRewriterID = VirtRegRewriter::ID; INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter", @@ -208,8 +221,6 @@ INITIALIZE_PASS_DEPENDENCY(VirtRegMap) INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter", "Virtual Register Rewriter", false, false) -char VirtRegRewriter::ID = 0; - void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<LiveIntervals>(); @@ -224,7 +235,6 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const { bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) { MF = &fn; - TM = &MF->getTarget(); TRI = MF->getSubtarget().getRegisterInfo(); TII = MF->getSubtarget().getInstrInfo(); MRI = &MF->getRegInfo(); @@ -260,8 +270,9 @@ void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI, assert(!LI.empty()); assert(LI.hasSubRanges()); - typedef std::pair<const LiveInterval::SubRange *, - LiveInterval::const_iterator> SubRangeIteratorPair; + using SubRangeIteratorPair = + std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>; + SmallVector<SubRangeIteratorPair, 4> SubRanges; SlotIndex First; SlotIndex Last; @@ -369,8 +380,8 @@ void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const { ++NumIdCopies; // Copies like: - // %R0 = COPY %R0<undef> - // %AL = COPY %AL, %EAX<imp-def> + // %r0 = COPY undef %r0 + // %al = COPY %al, implicit-def %eax // give us additional liveness information: The target (super-)register // must not be valid before this point. Replace the COPY with a KILL // instruction to maintain this information. @@ -477,7 +488,7 @@ void VirtRegRewriter::rewrite() { if (SubReg != 0) { if (NoSubRegLiveness) { // A virtual register kill refers to the whole register, so we may - // have to add <imp-use,kill> operands for the super-register. A + // have to add implicit killed operands for the super-register. A // partial redef always kills and redefines the super-register. if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) @@ -502,9 +513,9 @@ void VirtRegRewriter::rewrite() { } } - // The <def,undef> and <def,internal> flags only make sense for + // The def undef and def internal flags only make sense for // sub-register defs, and we are substituting a full physreg. An - // <imp-use,kill> operand from the SuperKills list will represent the + // implicit killed operand from the SuperKills list will represent the // partial read of the super-register. if (MO.isDef()) { MO.setIsUndef(false); @@ -519,6 +530,7 @@ void VirtRegRewriter::rewrite() { // Rewrite. Note we could have used MachineOperand::substPhysReg(), but // we need the inlining here. MO.setReg(PhysReg); + MO.setIsRenamableIfNoExtraRegAllocReq(); } // Add any missing super-register kills after rewriting the whole |