diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86')
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86.td | 14 | ||||
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp | 4 | ||||
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 2 | ||||
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86Subtarget.cpp | 2 | ||||
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86Subtarget.h | 8 |
6 files changed, 15 insertions, 17 deletions
diff --git a/contrib/llvm/lib/Target/X86/X86.td b/contrib/llvm/lib/Target/X86/X86.td index ab3319afe93f..30b3b2876b8a 100644 --- a/contrib/llvm/lib/Target/X86/X86.td +++ b/contrib/llvm/lib/Target/X86/X86.td @@ -132,9 +132,9 @@ def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", "Enable XOP instructions", [FeatureFMA4]>; -def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", - "HasVectorUAMem", "true", - "Allow unaligned memory operands on vector/SIMD instructions">; +def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", + "HasSSEUnalignedMem", "true", + "Allow unaligned memory operands with SSE instructions">; def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES instructions", [FeatureSSE2]>; @@ -309,7 +309,6 @@ class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ FeatureCMPXCHG16B, FeatureFastUAMem, FeatureSlowUAMem32, - FeatureVectorUAMem, FeaturePOPCNT, FeatureAES, FeaturePCLMUL @@ -322,7 +321,6 @@ class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ FeatureCMPXCHG16B, FeatureFastUAMem, FeatureSlowUAMem32, - FeatureVectorUAMem, FeaturePOPCNT, FeatureAES, FeaturePCLMUL, @@ -337,7 +335,6 @@ class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [ FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, - FeatureVectorUAMem, FeaturePOPCNT, FeatureAES, FeaturePCLMUL, @@ -360,7 +357,6 @@ class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [ FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, - FeatureVectorUAMem, FeaturePOPCNT, FeatureAES, FeaturePCLMUL, @@ -388,7 +384,7 @@ class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE, - FeatureSlowIncDec, FeatureVectorUAMem]>; + FeatureSlowIncDec]>; def : KnightsLandingProc<"knl">; // FIXME: define SKX model @@ -399,7 +395,7 @@ class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE, - FeatureSlowIncDec, FeatureSGX, FeatureVectorUAMem]>; + FeatureSlowIncDec, FeatureSGX]>; def : SkylakeProc<"skylake">; def : SkylakeProc<"skx">; // Legacy alias. diff --git a/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp b/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp index 14a0f38df668..d06e94fbfe1f 100644 --- a/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp +++ b/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp @@ -688,11 +688,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { std::vector<const MCSymbol*> DLLExportedFns, DLLExportedGlobals; for (const auto &Function : M) - if (Function.hasDLLExportStorageClass()) + if (Function.hasDLLExportStorageClass() && !Function.isDeclaration()) DLLExportedFns.push_back(getSymbol(&Function)); for (const auto &Global : M.globals()) - if (Global.hasDLLExportStorageClass()) + if (Global.hasDLLExportStorageClass() && !Global.isDeclaration()) DLLExportedGlobals.push_back(getSymbol(&Global)); for (const auto &Alias : M.aliases()) { diff --git a/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp b/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp index a1fd34ea8000..78a11e64fef0 100644 --- a/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5473,6 +5473,8 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) { DecodePSHUFBMask(C, Mask); + if (Mask.empty()) + return false; break; } diff --git a/contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index 76e8fad78de3..7069bd68e00e 100644 --- a/contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/contrib/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -424,7 +424,7 @@ def alignedloadv8i64 : PatFrag<(ops node:$ptr), // setting a feature bit in the processor (on startup, for example). // Opteron 10h and later implement such a feature. def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return Subtarget->hasVectorUAMem() + return Subtarget->hasSSEUnalignedMem() || cast<LoadSDNode>(N)->getAlignment() >= 16; }]>; diff --git a/contrib/llvm/lib/Target/X86/X86Subtarget.cpp b/contrib/llvm/lib/Target/X86/X86Subtarget.cpp index e59395c06a5c..983169886ad3 100644 --- a/contrib/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/contrib/llvm/lib/Target/X86/X86Subtarget.cpp @@ -265,7 +265,7 @@ void X86Subtarget::initializeEnvironment() { IsSHLDSlow = false; IsUAMemFast = false; IsUAMem32Slow = false; - HasVectorUAMem = false; + HasSSEUnalignedMem = false; HasCmpxchg16b = false; UseLeaForSP = false; HasSlowDivide32 = false; diff --git a/contrib/llvm/lib/Target/X86/X86Subtarget.h b/contrib/llvm/lib/Target/X86/X86Subtarget.h index 754b5b924717..e0263d66e928 100644 --- a/contrib/llvm/lib/Target/X86/X86Subtarget.h +++ b/contrib/llvm/lib/Target/X86/X86Subtarget.h @@ -162,9 +162,9 @@ protected: /// True if unaligned 32-byte memory accesses are slow. bool IsUAMem32Slow; - /// HasVectorUAMem - True if SIMD operations can have unaligned memory - /// operands. This may require setting a feature bit in the processor. - bool HasVectorUAMem; + /// True if SSE operations can have unaligned memory operands. + /// This may require setting a configuration bit in the processor. + bool HasSSEUnalignedMem; /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; /// this is true for most x86-64 chips, but not the first AMD chips. @@ -378,7 +378,7 @@ public: bool isSHLDSlow() const { return IsSHLDSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } - bool hasVectorUAMem() const { return HasVectorUAMem; } + bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } bool hasCmpxchg16b() const { return HasCmpxchg16b; } bool useLeaForSP() const { return UseLeaForSP; } bool hasSlowDivide32() const { return HasSlowDivide32; } |