diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/X86Schedule.td')
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86Schedule.td | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/contrib/llvm/lib/Target/X86/X86Schedule.td b/contrib/llvm/lib/Target/X86/X86Schedule.td index a261356afe6a..35257f89100c 100644 --- a/contrib/llvm/lib/Target/X86/X86Schedule.td +++ b/contrib/llvm/lib/Target/X86/X86Schedule.td @@ -364,6 +364,8 @@ def IIC_SSE_PALIGNRR : InstrItinClass; def IIC_SSE_PALIGNRM : InstrItinClass; def IIC_SSE_MWAIT : InstrItinClass; def IIC_SSE_MONITOR : InstrItinClass; +def IIC_SSE_MWAITX : InstrItinClass; +def IIC_SSE_MONITORX : InstrItinClass; def IIC_SSE_PREFETCH : InstrItinClass; def IIC_SSE_PAUSE : InstrItinClass; @@ -633,13 +635,22 @@ def IIC_NOP : InstrItinClass; // latencies. Since these latencies are not used for pipeline hazards, // they do not need to be exact. // -// The GenericModel contains no instruction itineraries. -def GenericModel : SchedMachineModel { +// The GenericX86Model contains no instruction itineraries +// and disables PostRAScheduler. +class GenericX86Model : SchedMachineModel { let IssueWidth = 4; let MicroOpBufferSize = 32; let LoadLatency = 4; let HighLatency = 10; let PostRAScheduler = 0; + let CompleteModel = 0; +} + +def GenericModel : GenericX86Model; + +// Define a model with the PostRAScheduler enabled. +def GenericPostRAModel : GenericX86Model { + let PostRAScheduler = 1; } include "X86ScheduleAtom.td" |