diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 351135079217..6af1f10189df 100644 --- a/contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -57,7 +57,10 @@ const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( switch (RC.getID()) { case Mips::GPR32RegClassID: case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: + case Mips::GPRMM16MovePPairFirstRegClassID: + case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID: case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: + case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID: case Mips::SP32RegClassID: return getRegBank(Mips::GPRBRegBankID); default: @@ -84,6 +87,16 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_LOAD: case G_STORE: case G_GEP: + case G_AND: + case G_OR: + case G_XOR: + case G_SHL: + case G_ASHR: + case G_LSHR: + case G_SDIV: + case G_UDIV: + case G_SREM: + case G_UREM: OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; break; case G_CONSTANT: @@ -92,6 +105,19 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); break; + case G_ICMP: + OperandsMapping = + getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, + &Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx]}); + break; + case G_SELECT: + OperandsMapping = + getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx]}); + break; default: return getInvalidInstructionMapping(); } |