diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp')
-rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 28 |
1 files changed, 12 insertions, 16 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 2c75e9139ad7..ddfda7e27793 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -97,6 +97,10 @@ static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print", static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization")); +static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", + cl::Hidden, cl::ZeroOrMore, cl::init(true), + cl::desc("Simplify the CFG after atomic expansion pass")); + /// HexagonTargetMachineModule - Note that this is used on hosts that /// cannot link in a library unless there are references into the /// library. In particular, it seems that it is not possible to get @@ -149,7 +153,6 @@ namespace llvm { FunctionPass *createHexagonCopyToCombine(); FunctionPass *createHexagonEarlyIfConversion(); FunctionPass *createHexagonFixupHwLoops(); - FunctionPass *createHexagonGatherPacketize(); FunctionPass *createHexagonGenExtract(); FunctionPass *createHexagonGenInsert(); FunctionPass *createHexagonGenMux(); @@ -161,7 +164,7 @@ namespace llvm { FunctionPass *createHexagonNewValueJump(); FunctionPass *createHexagonOptimizeSZextends(); FunctionPass *createHexagonOptAddrMode(); - FunctionPass *createHexagonPacketizer(); + FunctionPass *createHexagonPacketizer(bool Minimal); FunctionPass *createHexagonPeephole(); FunctionPass *createHexagonRDFOpt(); FunctionPass *createHexagonSplitConst32AndConst64(); @@ -177,12 +180,6 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } -static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { - if (CM) - return *CM; - return CodeModel::Small; -} - extern "C" void LLVMInitializeHexagonTarget() { // Register the target. RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget()); @@ -219,7 +216,8 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", TT, CPU, FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)), + getEffectiveCodeModel(CM, CodeModel::Small), + (HexagonNoOpt ? CodeGenOpt::None : OL)), TLOF(make_unique<HexagonTargetObjectFile>()) { initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); initAsmInfo(); @@ -311,7 +309,10 @@ void HexagonPassConfig::addIRPasses() { } addPass(createAtomicExpandPass()); + if (!NoOpt) { + if (EnableInitialCFGCleanup) + addPass(createCFGSimplificationPass(1, true, true, false, true)); if (EnableLoopPrefetch) addPass(createLoopDataPrefetchPass()); if (EnableCommGEP) @@ -402,7 +403,6 @@ void HexagonPassConfig::addPreEmitPass() { addPass(createHexagonBranchRelaxation()); - // Create Packets. if (!NoOpt) { if (!DisableHardwareLoops) addPass(createHexagonFixupHwLoops()); @@ -411,12 +411,8 @@ void HexagonPassConfig::addPreEmitPass() { addPass(createHexagonGenMux()); } - // Create packets for 2 instructions that consitute a gather instruction. - // Do this regardless of the opt level. - addPass(createHexagonGatherPacketize(), false); - - if (!NoOpt) - addPass(createHexagonPacketizer(), false); + // Packetization is mandatory: it handles gather/scatter at all opt levels. + addPass(createHexagonPacketizer(NoOpt), false); if (EnableVectorPrint) addPass(createHexagonVectorPrint(), false); |