diff options
Diffstat (limited to 'contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td | 89 |
1 files changed, 56 insertions, 33 deletions
diff --git a/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td b/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td index f67075fbf9fd..7a6673b49d57 100644 --- a/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1775,7 +1775,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin, let hasSideEffects = 0 in { -let mayLoad = 1, hasExtraDefRegAllocReq = 1 in +let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; multiclass thumb2_st_mult<string asm, InstrItinClass itin, @@ -1997,6 +1997,10 @@ def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn), (t2SXTB16 rGPR:$Rn, 0)>; def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm), (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; +def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), + (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>; +def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), + (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; // A simple right-shift can also be used in most cases (the exception is the @@ -2032,6 +2036,8 @@ def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF), def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm), (t2UXTB16 rGPR:$Rm, 0)>; +def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), + (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>; // FIXME: This pattern incorrectly assumes the shl operator is a rotate. // The transformation should probably be done as a combiner action @@ -2062,6 +2068,8 @@ def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm), (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; +def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), + (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; } @@ -2086,6 +2094,12 @@ defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>; defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>; defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>; +def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm), + (t2SUBSri $Rn, t2_so_imm:$imm)>; +def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>; +def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm), + (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>; + let hasPostISelHook = 1 in { defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>; defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>; @@ -2718,28 +2732,25 @@ class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc, } def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb", - [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), - (sext_inreg rGPR:$Rm, i16)))]>; + [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>; def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt", - [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), - (sra rGPR:$Rm, (i32 16))))]>; + [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>; def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb", - [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)), - (sext_inreg rGPR:$Rm, i16)))]>; + [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>; def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt", - [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)), - (sra rGPR:$Rm, (i32 16))))]>; + [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>; def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>; def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>; -def : Thumb2DSPPat<(mul sext_16_node:$Rm, sext_16_node:$Rn), - (t2SMULBB rGPR:$Rm, rGPR:$Rn)>; -def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16))), +def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)), + (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; +def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)), (t2SMULBT rGPR:$Rn, rGPR:$Rm)>; -def : Thumb2DSPPat<(mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm), +def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm), (t2SMULTB rGPR:$Rn, rGPR:$Rm)>; + def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm), (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm), @@ -2767,18 +2778,13 @@ class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc, } def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb", - [(set rGPR:$Rd, (add rGPR:$Ra, - (mul (sext_inreg rGPR:$Rn, i16), - (sext_inreg rGPR:$Rm, i16))))]>; + [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>; def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt", - [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16), - (sra rGPR:$Rm, (i32 16)))))]>; + [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>; def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb", - [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), - (sext_inreg rGPR:$Rm, i16))))]>; + [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>; def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt", - [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), - (sra rGPR:$Rm, (i32 16)))))]>; + [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>; def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>; def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", @@ -2786,11 +2792,14 @@ def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)), (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; -def : Thumb2DSPMulPat<(add rGPR:$Ra, - (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16)))), +def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, + (sext_bottom_16 rGPR:$Rm))), + (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; +def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, + (sext_top_16 rGPR:$Rm))), (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; -def : Thumb2DSPMulPat<(add rGPR:$Ra, - (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm)), +def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn), + sext_16_node:$Rm)), (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), @@ -3223,6 +3232,14 @@ def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary, } } +// Armv8.5-A speculation barrier +def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>, + Requires<[IsThumb2, HasSB]>, Sched<[]> { + let Inst{31-0} = 0xf3bf8f70; + let Unpredictable = 0x000f2f0f; + let hasSideEffects = 1; +} + class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, InstrItinClass itin, string opc, string asm, string cstr, list<dag> pattern, bits<4> rt2 = 0b1111> @@ -4429,13 +4446,13 @@ def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; -let AddedComplexity = 8 in { - def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>; - def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>; - def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>; - def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>; - def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>; - def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>; +let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in { + def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>; + def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>; + def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>; + def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>; + def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>; + def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>; } @@ -4538,6 +4555,12 @@ def : t2InstAlias<"tst${p} $Rn, $Rm", def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>; def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>; def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>; + +// Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where +// 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR". +def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; +def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; + // Armv8-R 'Data Full Barrier' def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>; |