diff options
Diffstat (limited to 'contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h')
-rw-r--r-- | contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h | 56 |
1 files changed, 20 insertions, 36 deletions
diff --git a/contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h index 62644ab2f457..688ca755d0b5 100644 --- a/contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ b/contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -16,6 +16,7 @@ #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/bit.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include <cassert> @@ -342,27 +343,23 @@ static inline bool isValidDecodeLogicalImmediate(uint64_t val, // static inline float getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. - union { - uint32_t I; - float F; - } FPUnion; uint8_t Sign = (Imm >> 7) & 0x1; uint8_t Exp = (Imm >> 4) & 0x7; uint8_t Mantissa = Imm & 0xf; - // 8-bit FP iEEEE Float Encoding + // 8-bit FP IEEE Float Encoding // abcd efgh aBbbbbbc defgh000 00000000 00000000 // // where B = NOT(b); - FPUnion.I = 0; - FPUnion.I |= Sign << 31; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; - FPUnion.I |= (Exp & 0x3) << 23; - FPUnion.I |= Mantissa << 19; - return FPUnion.F; + uint32_t I = 0; + I |= Sign << 31; + I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + I |= (Exp & 0x3) << 23; + I |= Mantissa << 19; + return bit_cast<float>(I); } /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit @@ -757,12 +754,8 @@ static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) { /// Returns true if Imm is the concatenation of a repeating pattern of type T. template <typename T> static inline bool isSVEMaskOfIdenticalElements(int64_t Imm) { - union { - int64_t Whole; - T Parts[sizeof(int64_t)/sizeof(T)]; - } Vec { Imm }; - - return all_of(Vec.Parts, [Vec](T Elem) { return Elem == Vec.Parts[0]; }); + auto Parts = bit_cast<std::array<T, sizeof(int64_t) / sizeof(T)>>(Imm); + return all_of(Parts, [&](T Elem) { return Elem == Parts[0]; }); } /// Returns true if Imm is valid for CPY/DUP. @@ -790,29 +783,20 @@ static inline bool isSVEAddSubImm(int64_t Imm) { /// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. static inline bool isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) { - union { - int64_t D; - int32_t S[2]; - int16_t H[4]; - int8_t B[8]; - } Vec = { Imm }; - - if (isSVECpyImm<int64_t>(Vec.D)) + if (isSVECpyImm<int64_t>(Imm)) return false; - if (isSVEMaskOfIdenticalElements<int32_t>(Imm) && - isSVECpyImm<int32_t>(Vec.S[0])) - return false; + auto S = bit_cast<std::array<int32_t, 2>>(Imm); + auto H = bit_cast<std::array<int16_t, 4>>(Imm); + auto B = bit_cast<std::array<int8_t, 8>>(Imm); - if (isSVEMaskOfIdenticalElements<int16_t>(Imm) && - isSVECpyImm<int16_t>(Vec.H[0])) + if (isSVEMaskOfIdenticalElements<int32_t>(Imm) && isSVECpyImm<int32_t>(S[0])) return false; - - if (isSVEMaskOfIdenticalElements<int8_t>(Imm) && - isSVECpyImm<int8_t>(Vec.B[0])) + if (isSVEMaskOfIdenticalElements<int16_t>(Imm) && isSVECpyImm<int16_t>(H[0])) return false; - - return isLogicalImmediate(Vec.D, 64); + if (isSVEMaskOfIdenticalElements<int8_t>(Imm) && isSVECpyImm<int8_t>(B[0])) + return false; + return isLogicalImmediate(Imm, 64); } inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { |