diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td b/contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td index 4aea7bc253bb..d2ced1c67407 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -206,6 +206,10 @@ defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; +// Model the effect of clobbering the read-write mask operand of the GATHER operation. +// Does not cost anything by itself, only has latency, matching that of the WriteLoad, +defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; + // Idioms that clear a register, like xorps %xmm0, %xmm0. // These can often bypass execution ports completely. def : WriteRes<WriteZero, []>; @@ -582,6 +586,7 @@ def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def Writ defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. +defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>; // 256-bit width packed vector width-changing move. defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. // Old microcoded instructions that nobody use. |