diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td | 49 |
1 files changed, 21 insertions, 28 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td index a6fcc804e1d0..cf57fe562ed5 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSSE.td @@ -3212,13 +3212,13 @@ let Predicates = [UseSSE2] in { // Prefetch intrinsic. let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in { def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src), - "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB; + "prefetcht0\t$src", [(prefetch addr:$src, timm, (i32 3), (i32 1))]>, TB; def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src), - "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB; + "prefetcht1\t$src", [(prefetch addr:$src, timm, (i32 2), (i32 1))]>, TB; def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src), - "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB; + "prefetcht2\t$src", [(prefetch addr:$src, timm, (i32 1), (i32 1))]>, TB; def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src), - "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB; + "prefetchnta\t$src", [(prefetch addr:$src, timm, (i32 0), (i32 1))]>, TB; } // FIXME: How should flush instruction be modeled? @@ -7093,35 +7093,35 @@ def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256, // halves of a 256-bit vector. // let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in -def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst), - (ins i128mem:$src), - "vbroadcasti128\t{$src, $dst|$dst, $src}", []>, - Sched<[WriteShuffleLd]>, VEX, VEX_L; +def VBROADCASTI128rm : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst), + (ins i128mem:$src), + "vbroadcasti128\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteShuffleLd]>, VEX, VEX_L; let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX], ExeDomain = SSEPackedSingle in -def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst), - (ins f128mem:$src), - "vbroadcastf128\t{$src, $dst|$dst, $src}", []>, - Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L; +def VBROADCASTF128rm : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst), + (ins f128mem:$src), + "vbroadcastf128\t{$src, $dst|$dst, $src}", []>, + Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L; let Predicates = [HasAVX, NoVLX] in { def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; def : Pat<(v8f32 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; // NOTE: We're using FP instructions here, but execution domain fixing can // convert to integer when profitable. def : Pat<(v4i64 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; def : Pat<(v8i32 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; def : Pat<(v16f16 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; def : Pat<(v32i8 (X86SubVBroadcastld128 addr:$src)), - (VBROADCASTF128 addr:$src)>; + (VBROADCASTF128rm addr:$src)>; } //===----------------------------------------------------------------------===// @@ -7316,7 +7316,7 @@ defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd", // AVX_VNNI //===----------------------------------------------------------------------===// let Predicates = [HasAVXVNNI, NoVLX_Or_NoVNNI], Constraints = "$src1 = $dst", - ExplicitVEXPrefix = 1, checkVEXPredicate = 1 in + explicitOpPrefix = ExplicitVEX in multiclass avx_vnni_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, bit IsCommutable> { let isCommutable = IsCommutable in @@ -7359,11 +7359,6 @@ defm VPDPBUSDS : avx_vnni_rm<0x51, "vpdpbusds", X86Vpdpbusds, 0>; defm VPDPWSSD : avx_vnni_rm<0x52, "vpdpwssd", X86Vpdpwssd, 1>; defm VPDPWSSDS : avx_vnni_rm<0x53, "vpdpwssds", X86Vpdpwssds, 1>; -def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs), - (X86vpmaddwd node:$lhs, node:$rhs), [{ - return N->hasOneUse(); -}]>; - let Predicates = [HasAVXVNNI, NoVLX_Or_NoVNNI] in { def : Pat<(v8i32 (add VR256:$src1, (X86vpmaddwd_su VR256:$src2, VR256:$src3))), @@ -8142,8 +8137,7 @@ let isCommutable = 0 in { } // AVX-IFMA -let Predicates = [HasAVXIFMA, NoVLX_Or_NoIFMA], Constraints = "$src1 = $dst", - checkVEXPredicate = 1 in +let Predicates = [HasAVXIFMA, NoVLX_Or_NoIFMA], Constraints = "$src1 = $dst" in multiclass avx_ifma_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // NOTE: The SDNode have the multiply operands first with the add last. // This enables commuted load patterns to be autogenerated by tablegen. @@ -8287,7 +8281,6 @@ let Predicates = [HasAVXNECONVERT] in { f256mem>, T8XD; defm VCVTNEOPH2PS : AVX_NE_CONVERT_BASE<0xb0, "vcvtneoph2ps", f128mem, f256mem>, T8PS; - let checkVEXPredicate = 1 in defm VCVTNEPS2BF16 : VCVTNEPS2BF16_BASE, VEX, T8XS, ExplicitVEXPrefix; def : Pat<(v8bf16 (X86vfpround (v8f32 VR256:$src))), |