diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 711ad4335ece..e452a84a9a6f 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -363,6 +363,91 @@ multiclass VPatNConvertFP2ISDNode_V<SDNode vop, string instruction_name> { } } +multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, string instruction_name> { + foreach vti = AllWidenableIntVectors in { + def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))), + (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), + (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX) + vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))), + (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), + (!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX) + vti.Vti.RegClass:$rs2, GPR:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), + (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), + (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), + (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), + (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rs2, GPR:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + } +} + +multiclass VPatWidenMulAddSDNode_VV<PatFrags extop1, PatFrags extop2, string instruction_name> { + foreach vti = AllWidenableIntVectors in { + def : Pat< + (add (vti.Wti.Vector vti.Wti.RegClass:$rd), + (mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector vti.Vti.RegClass:$rs1))), + (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))), + (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rd, vti.Vti.RegClass:$rs1, vti.Vti.RegClass:$rs2, + vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC + )>; + } +} +multiclass VPatWidenMulAddSDNode_VX<PatFrags extop1, PatFrags extop2, string instruction_name> { + foreach vti = AllWidenableIntVectors in { + def : Pat< + (add (vti.Wti.Vector vti.Wti.RegClass:$rd), + (mul_oneuse (vti.Wti.Vector (extop1 (vti.Vti.Vector (SplatPat GPR:$rs1)))), + (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))), + (!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rd, GPR:$rs1, vti.Vti.RegClass:$rs2, + vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC + )>; + } +} + +multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> { + foreach vti = AllWidenableFloatVectors in { + def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))), + (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), + (!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX) + vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))), + (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))), + (!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX) + vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + } +} + +multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> { + foreach vti = AllWidenableFloatVectors in { + def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), + (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), + (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2), + (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))), + (!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX) + vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1, + vti.Vti.AVL, vti.Vti.Log2SEW)>; + } +} + +multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> { + defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>; + defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>; +} + //===----------------------------------------------------------------------===// // Patterns. //===----------------------------------------------------------------------===// @@ -399,6 +484,15 @@ foreach vti = AllIntegerVectors in { vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; } +// 12.2. Vector Widening Integer Add and Subtract +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">; +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">; +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">; + +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">; +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">; +defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">; + // 12.3. Vector Integer Extension defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2", AllFractionableVF2IntVectors>; @@ -513,6 +607,15 @@ foreach vti = AllIntegerVectors in { vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; } +// 12.14 Vector Widening Integer Multiply-Add Instructions +defm : VPatWidenMulAddSDNode_VV<sext_oneuse, sext_oneuse, "PseudoVWMACC">; +defm : VPatWidenMulAddSDNode_VX<sext_oneuse, sext_oneuse, "PseudoVWMACC">; +defm : VPatWidenMulAddSDNode_VV<zext_oneuse, zext_oneuse, "PseudoVWMACCU">; +defm : VPatWidenMulAddSDNode_VX<zext_oneuse, zext_oneuse, "PseudoVWMACCU">; +defm : VPatWidenMulAddSDNode_VV<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">; +defm : VPatWidenMulAddSDNode_VX<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">; +defm : VPatWidenMulAddSDNode_VX<zext_oneuse, sext_oneuse, "PseudoVWMACCUS">; + // 12.15. Vector Integer Merge Instructions foreach vti = AllIntegerVectors in { def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1, @@ -582,11 +685,18 @@ defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">; defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">; defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">; +// 14.3. Vector Widening Floating-Point Add/Subtract Instructions +defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">; +defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">; + // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">; defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">; defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">; +// 14.5. Vector Widening Floating-Point Multiply Instructions +defm : VPatWidenBinaryFPSDNode_VV_VF<fmul, "PseudoVFWMUL">; + // 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. foreach fvti = AllFloatVectors in { // NOTE: We choose VFMADD because it has the most commuting freedom. So it |