diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index 281719c12e70..77e174135a59 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -30,7 +30,7 @@ public: RISCVDAGToDAGISel() = delete; explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, - CodeGenOpt::Level OptLevel) + CodeGenOptLevel OptLevel) : SelectionDAGISel(ID, TargetMachine, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -43,7 +43,8 @@ public: void Select(SDNode *Node) override; - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector<SDValue> &OutOps) override; bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset); @@ -53,6 +54,7 @@ public: bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset) { return SelectAddrRegImm(Addr, Base, Offset, true); } + bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset); bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale); @@ -134,7 +136,9 @@ public: } bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal); bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal); - bool selectExtOneUseVSplat(SDValue N, SDValue &SplatVal); + // Matches the splat of a value which can be extended or truncated, such that + // only the bottom 8 bits are preserved. + bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal); bool selectFPImm(SDValue N, SDValue &Imm); bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm); @@ -183,9 +187,9 @@ public: private: bool doPeepholeSExtW(SDNode *Node); - bool doPeepholeMaskedRVV(SDNode *Node); + bool doPeepholeMaskedRVV(MachineSDNode *Node); bool doPeepholeMergeVVMFold(); - bool performVMergeToVMv(SDNode *N); + bool doPeepholeNoRegPassThru(); bool performCombineVMergeAndVOps(SDNode *N); }; @@ -259,6 +263,7 @@ struct RISCVMaskedPseudoInfo { uint16_t MaskedPseudo; uint16_t UnmaskedPseudo; uint8_t MaskOpIdx; + uint8_t MaskAffectsResult : 1; }; #define GET_RISCVVSSEGTable_DECL |