diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc')
12 files changed, 317 insertions, 40 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 89d04dbe378e..251737ed1275 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -87,7 +87,8 @@ protected: Triple TT; public: PPCAsmBackend(const Target &T, const Triple &TT) - : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), + : MCAsmBackend(TT.isLittleEndian() ? llvm::endianness::little + : llvm::endianness::big), TT(TT) {} unsigned getNumFixupKinds() const override { @@ -132,7 +133,7 @@ public: assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); - return (Endian == support::little + return (Endian == llvm::endianness::little ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; } @@ -154,13 +155,15 @@ public: // from the fixup value. The Value has been "split up" into the appropriate // bitfields above. for (unsigned i = 0; i != NumBytes; ++i) { - unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i); + unsigned Idx = + Endian == llvm::endianness::little ? i : (NumBytes - 1 - i); Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); } } bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target) override { + const MCValue &Target, + const MCSubtargetInfo *STI) override { MCFixupKind Kind = Fixup.getKind(); switch ((unsigned)Kind) { default: diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index 1e58039582c2..6a72b7b9ad05 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -28,7 +28,7 @@ namespace { unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; - bool needsRelocateWithSymbol(const MCSymbol &Sym, + bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym, unsigned Type) const override; }; } @@ -456,7 +456,13 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, } break; case FK_Data_4: - Type = ELF::R_PPC_ADDR32; + switch (Modifier) { + case MCSymbolRefExpr::VK_DTPREL: + Type = ELF::R_PPC_DTPREL32; + break; + default: + Type = ELF::R_PPC_ADDR32; + } break; case FK_Data_2: Type = ELF::R_PPC_ADDR16; @@ -466,7 +472,8 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, return Type; } -bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, +bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCValue &, + const MCSymbol &Sym, unsigned Type) const { switch (Type) { default: diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp index 2f03aa37745f..1eaa57e16260 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp @@ -17,11 +17,10 @@ // //===----------------------------------------------------------------------===// - #include "PPCELFStreamer.h" #include "PPCFixupKinds.h" -#include "PPCInstrInfo.h" #include "PPCMCCodeEmitter.h" +#include "PPCMCTargetDesc.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h index 7d786ac13bb9..10204b184a49 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h @@ -13,7 +13,6 @@ #ifndef LLVM_LIB_TARGET_PPC_MCELFSTREAMER_PPCELFSTREAMER_H #define LLVM_LIB_TARGET_PPC_MCELFSTREAMER_PPCELFSTREAMER_H -#include "llvm/ADT/SmallVector.h" #include "llvm/MC/MCELFStreamer.h" #include <memory> diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 13480da4e731..9a4291c90408 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -13,14 +13,14 @@ #include "MCTargetDesc/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCPredicates.h" -#include "PPCInstrInfo.h" -#include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -484,7 +484,10 @@ void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo, if (!MI->getOperand(OpNo).isImm()) return printOperand(MI, OpNo, STI, O); - O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); + uint64_t Imm = static_cast<uint64_t>(MI->getOperand(OpNo).getImm()) << 2; + if (!TT.isPPC64()) + Imm = static_cast<uint32_t>(Imm); + O << formatHex(Imm); } void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, @@ -597,7 +600,8 @@ void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo, /// showRegistersWithPercentPrefix - Check if this register name should be /// printed with a percentage symbol as prefix. bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { - if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX) + if ((!FullRegNamesWithPercent && !MAI.useFullRegisterNames()) || + TT.getOS() == Triple::AIX) return false; switch (RegName[0]) { @@ -614,10 +618,10 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { /// getVerboseConditionalRegName - This method expands the condition register /// when requested explicitly or targetting Darwin. -const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) - const { - if (!FullRegNames) +const char * +PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, + unsigned RegEncoding) const { + if (!FullRegNames && !MAI.useFullRegisterNames()) return nullptr; if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN) return nullptr; @@ -637,7 +641,7 @@ const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, // showRegistersWithPrefix - This method determines whether registers // should be number-only or include the prefix. bool PPCInstPrinter::showRegistersWithPrefix() const { - return FullRegNamesWithPercent || FullRegNames; + return FullRegNamesWithPercent || FullRegNames || MAI.useFullRegisterNames(); } void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, @@ -646,8 +650,7 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, if (Op.isReg()) { unsigned Reg = Op.getReg(); if (!ShowVSRNumsAsVR) - Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()), - Reg, OpNo); + Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo); const char *RegName; RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); @@ -656,7 +659,7 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, if (showRegistersWithPercentPrefix(RegName)) O << "%"; if (!showRegistersWithPrefix()) - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); + RegName = PPC::stripRegisterPrefix(RegName); O << RegName; return; diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp index a5dc0b45b13c..4716e37b3443 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -12,7 +12,6 @@ #include "PPCMCAsmInfo.h" #include "llvm/TargetParser/Triple.h" -#include <cassert> using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index da0174ce1982..910b5892d033 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -12,12 +12,14 @@ #include "PPCMCCodeEmitter.h" #include "MCTargetDesc/PPCFixupKinds.h" -#include "PPCInstrInfo.h" +#include "PPCMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" #include "llvm/Support/ErrorHandling.h" @@ -47,16 +49,108 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo *>(&MCII); - unsigned Opcode = MI.getOpcode(); // Add a fixup for the branch target. Fixups.push_back(MCFixup::create(0, MO.getExpr(), - (InstrInfo->isNoTOCCallInstr(Opcode) + (isNoTOCCallInstr(MI) ? (MCFixupKind)PPC::fixup_ppc_br24_notoc : (MCFixupKind)PPC::fixup_ppc_br24))); return 0; } +/// Check if Opcode corresponds to a call instruction that should be marked +/// with the NOTOC relocation. +bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const { + unsigned Opcode = MI.getOpcode(); + if (!MCII.get(Opcode).isCall()) + return false; + + switch (Opcode) { + default: +#ifndef NDEBUG + llvm_unreachable("Unknown call opcode"); +#endif + return false; + case PPC::BL8_NOTOC: + case PPC::BL8_NOTOC_TLS: + case PPC::BL8_NOTOC_RM: + return true; +#ifndef NDEBUG + case PPC::BL8: + case PPC::BL: + case PPC::BL8_TLS: + case PPC::BL_TLS: + case PPC::BLA8: + case PPC::BLA: + case PPC::BCCL: + case PPC::BCCLA: + case PPC::BCL: + case PPC::BCLn: + case PPC::BL8_NOP: + case PPC::BL_NOP: + case PPC::BL8_NOP_TLS: + case PPC::BLA8_NOP: + case PPC::BCTRL8: + case PPC::BCTRL: + case PPC::BCCCTRL8: + case PPC::BCCCTRL: + case PPC::BCCTRL8: + case PPC::BCCTRL: + case PPC::BCCTRL8n: + case PPC::BCCTRLn: + case PPC::BL8_RM: + case PPC::BLA8_RM: + case PPC::BL8_NOP_RM: + case PPC::BLA8_NOP_RM: + case PPC::BCTRL8_RM: + case PPC::BCTRL8_LDinto_toc: + case PPC::BCTRL8_LDinto_toc_RM: + case PPC::BL8_TLS_: + case PPC::TCRETURNdi8: + case PPC::TCRETURNai8: + case PPC::TCRETURNri8: + case PPC::TAILBCTR8: + case PPC::TAILB8: + case PPC::TAILBA8: + case PPC::BCLalways: + case PPC::BLRL: + case PPC::BCCLRL: + case PPC::BCLRL: + case PPC::BCLRLn: + case PPC::BDZL: + case PPC::BDNZL: + case PPC::BDZLA: + case PPC::BDNZLA: + case PPC::BDZLp: + case PPC::BDNZLp: + case PPC::BDZLAp: + case PPC::BDNZLAp: + case PPC::BDZLm: + case PPC::BDNZLm: + case PPC::BDZLAm: + case PPC::BDNZLAm: + case PPC::BDZLRL: + case PPC::BDNZLRL: + case PPC::BDZLRLp: + case PPC::BDNZLRLp: + case PPC::BDZLRLm: + case PPC::BDNZLRLm: + case PPC::BL_RM: + case PPC::BLA_RM: + case PPC::BL_NOP_RM: + case PPC::BCTRL_RM: + case PPC::TCRETURNdi: + case PPC::TCRETURNai: + case PPC::TCRETURNri: + case PPC::BCTRL_LWZinto_toc: + case PPC::BCTRL_LWZinto_toc_RM: + case PPC::TAILBCTR: + case PPC::TAILB: + case PPC::TAILBA: + return false; +#endif + } +} + unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { @@ -372,7 +466,7 @@ get_crbitm_encoding(const MCInst &MI, unsigned OpNo, } // Get the index for this operand in this instruction. This is needed for -// computing the register number in PPCInstrInfo::getRegNumForOperand() for +// computing the register number in PPC::getRegNumForOperand() for // any instructions that use a different numbering scheme for registers in // different operands. static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) { @@ -397,8 +491,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); unsigned OpNo = getOpIdxForMO(MI, MO); unsigned Reg = - PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()), - MO.getReg(), OpNo); + PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo); return CTX.getRegisterInfo()->getEncodingValue(Reg); } @@ -415,7 +508,8 @@ void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, // Output the constant in big/little endian byte order. unsigned Size = getInstSizeInBytes(MI); - support::endianness E = IsLittleEndian ? support::little : support::big; + llvm::endianness E = + IsLittleEndian ? llvm::endianness::little : llvm::endianness::big; switch (Size) { case 0: break; @@ -443,9 +537,7 @@ unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const { } bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const { - unsigned Opcode = MI.getOpcode(); - const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII); - return InstrInfo->isPrefixed(Opcode); + return MCII.get(MI.getOpcode()).TSFlags & PPCII::Prefixed; } #include "PPCGenMCCodeEmitter.inc" diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h index 17a15ef18cb7..b57455718319 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h @@ -121,6 +121,10 @@ public: // Is this instruction a prefixed instruction. bool isPrefixedInstruction(const MCInst &MI) const; + + /// Check if Opcode corresponds to a call instruction that should be marked + /// with the NOTOC relocation. + bool isNoTOCCallInstr(const MCInst &MI) const; }; } // namespace llvm diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 271f7ab757e1..a804dd823daa 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -57,6 +57,90 @@ using namespace llvm; #define GET_REGINFO_MC_DESC #include "PPCGenRegisterInfo.inc" +/// stripRegisterPrefix - This method strips the character prefix from a +/// register name so that only the number is left. Used by for linux asm. +const char *PPC::stripRegisterPrefix(const char *RegName) { + switch (RegName[0]) { + case 'a': + if (RegName[1] == 'c' && RegName[2] == 'c') + return RegName + 3; + break; + case 'f': + if (RegName[1] == 'p') + return RegName + 2; + [[fallthrough]]; + case 'r': + case 'v': + if (RegName[1] == 's') { + if (RegName[2] == 'p') + return RegName + 3; + return RegName + 2; + } + return RegName + 1; + case 'c': + if (RegName[1] == 'r') + return RegName + 2; + break; + case 'w': + // For wacc and wacc_hi + if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') { + if (RegName[4] == '_') + return RegName + 7; + else + return RegName + 4; + } + break; + case 'd': + // For dmr, dmrp, dmrrow, dmrrowp + if (RegName[1] == 'm' && RegName[2] == 'r') { + if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' && + RegName[6] == 'p') + return RegName + 7; + else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w') + return RegName + 6; + else if (RegName[3] == 'p') + return RegName + 4; + else + return RegName + 3; + } + break; + } + + return RegName; +} + +/// getRegNumForOperand - some operands use different numbering schemes +/// for the same registers. For example, a VSX instruction may have any of +/// vs0-vs63 allocated whereas an Altivec instruction could only have +/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual +/// register number needed for the opcode/operand number combination. +/// The operand number argument will be useful when we need to extend this +/// to instructions that use both Altivec and VSX numbering (for different +/// operands). +unsigned PPC::getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, + unsigned OpNo) { + int16_t regClass = Desc.operands()[OpNo].RegClass; + switch (regClass) { + // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, + // VSX32-VSX63 during encoding/disassembling + case PPC::VSSRCRegClassID: + case PPC::VSFRCRegClassID: + if (PPC::isVFRegister(Reg)) + return PPC::VSX32 + (Reg - PPC::VF0); + break; + // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, + // VSX32-VSX63 during encoding/disassembling + case PPC::VSRCRegClassID: + if (PPC::isVRRegister(Reg)) + return PPC::VSX32 + (Reg - PPC::V0); + break; + // Other RegClass doesn't need mapping + default: + break; + } + return Reg; +} + PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} // Pin the vtable to this file. @@ -148,9 +232,10 @@ public: cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly()) ->getQualNameSymbol(); // On AIX, we have a region handle (symbol@m) and the variable offset - // (symbol@{gd|le}) for TLS variables, depending on the TLS model. + // (symbol@{gd|ie|le}) for TLS variables, depending on the TLS model. if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD || Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM || + Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE || Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE) OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@" << MCSymbolRefExpr::getVariantKindName(Kind) << '\n'; diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h index 86ca1386fed9..16777725990a 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -26,6 +26,7 @@ namespace llvm { class MCAsmBackend; class MCCodeEmitter; class MCContext; +class MCInstrDesc; class MCInstrInfo; class MCObjectTargetWriter; class MCRegisterInfo; @@ -33,6 +34,24 @@ class MCSubtargetInfo; class MCTargetOptions; class Target; +namespace PPC { +/// stripRegisterPrefix - This method strips the character prefix from a +/// register name so that only the number is left. Used by for linux asm. +const char *stripRegisterPrefix(const char *RegName); + +/// getRegNumForOperand - some operands use different numbering schemes +/// for the same registers. For example, a VSX instruction may have any of +/// vs0-vs63 allocated whereas an Altivec instruction could only have +/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual +/// register number needed for the opcode/operand number combination. +/// The operand number argument will be useful when we need to extend this +/// to instructions that use both Altivec and VSX numbering (for different +/// operands). +unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, + unsigned OpNo); + +} // namespace PPC + MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); @@ -102,11 +121,61 @@ static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) { return false; } -} // end namespace llvm +/// PPCII - This namespace holds all of the PowerPC target-specific +/// per-instruction flags. These must match the corresponding definitions in +/// PPC.td and PPCInstrFormats.td. +namespace PPCII { +enum { + // PPC970 Instruction Flags. These flags describe the characteristics of the + // PowerPC 970 (aka G5) dispatch groups and how they are formed out of + // raw machine instructions. -// Generated files will use "namespace PPC". To avoid symbol clash, -// undefine PPC here. PPC may be predefined on some hosts. -#undef PPC + /// PPC970_First - This instruction starts a new dispatch group, so it will + /// always be the first one in the group. + PPC970_First = 0x1, + + /// PPC970_Single - This instruction starts a new dispatch group and + /// terminates it, so it will be the sole instruction in the group. + PPC970_Single = 0x2, + + /// PPC970_Cracked - This instruction is cracked into two pieces, requiring + /// two dispatch pipes to be available to issue. + PPC970_Cracked = 0x4, + + /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that + /// an instruction is issued to. + PPC970_Shift = 3, + PPC970_Mask = 0x07 << PPC970_Shift +}; +enum PPC970_Unit { + /// These are the various PPC970 execution unit pipelines. Each instruction + /// is one of these. + PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction + PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit + PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit + PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit + PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit + PPC970_VALU = 5 << PPC970_Shift, // Vector ALU + PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit + PPC970_BRU = 7 << PPC970_Shift // Branch Unit +}; + +enum { + /// Shift count to bypass PPC970 flags + NewDef_Shift = 6, + + /// This instruction is an X-Form memory operation. + XFormMemOp = 0x1 << NewDef_Shift, + /// This instruction is prefixed. + Prefixed = 0x1 << (NewDef_Shift + 1), + /// This instruction produced a sign extended result. + SExt32To64 = 0x1 << (NewDef_Shift + 2), + /// This instruction produced a zero extended result. + ZExt32To64 = 0x1 << (NewDef_Shift + 3) +}; +} // end namespace PPCII + +} // end namespace llvm // Defines symbolic names for PowerPC registers. This defines a mapping from // register name to register number. @@ -214,4 +283,16 @@ using llvm::MCPhysReg; static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \ static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp); +namespace llvm { +namespace PPC { +static inline bool isVFRegister(unsigned Reg) { + return Reg >= PPC::VF0 && Reg <= PPC::VF31; +} + +static inline bool isVRRegister(unsigned Reg) { + return Reg >= PPC::V0 && Reg <= PPC::V31; +} +} // namespace PPC +} // namespace llvm + #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp index 284e52c298a2..80c37f82bf29 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp @@ -12,7 +12,6 @@ #include "PPCPredicates.h" #include "llvm/Support/ErrorHandling.h" -#include <cassert> using namespace llvm; PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp index df671f53cbd8..065daf42fe6e 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp @@ -69,6 +69,8 @@ std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize( return {XCOFF::RelocationType::R_TOCU, SignAndSizeForHalf16}; case MCSymbolRefExpr::VK_PPC_L: return {XCOFF::RelocationType::R_TOCL, SignAndSizeForHalf16}; + case MCSymbolRefExpr::VK_PPC_AIX_TLSLE: + return {XCOFF::RelocationType::R_TLS_LE, SignAndSizeForHalf16}; } } break; case PPC::fixup_ppc_half16ds: @@ -82,6 +84,8 @@ std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize( return {XCOFF::RelocationType::R_TOC, 15}; case MCSymbolRefExpr::VK_PPC_L: return {XCOFF::RelocationType::R_TOCL, 15}; + case MCSymbolRefExpr::VK_PPC_AIX_TLSLE: + return {XCOFF::RelocationType::R_TLS_LE, 15}; } } break; case PPC::fixup_ppc_br24: @@ -108,6 +112,8 @@ std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize( return {XCOFF::RelocationType::R_TLS, SignAndSizeForFKData}; case MCSymbolRefExpr::VK_PPC_AIX_TLSGDM: return {XCOFF::RelocationType::R_TLSM, SignAndSizeForFKData}; + case MCSymbolRefExpr::VK_PPC_AIX_TLSIE: + return {XCOFF::RelocationType::R_TLS_IE, SignAndSizeForFKData}; case MCSymbolRefExpr::VK_PPC_AIX_TLSLE: return {XCOFF::RelocationType::R_TLS_LE, SignAndSizeForFKData}; case MCSymbolRefExpr::VK_None: |