diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 3e7d4d81b242..e8b5f6059c9e 100644 --- a/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -738,11 +738,13 @@ def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>; def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; +def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>; def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>; +def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>; def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; @@ -1927,3 +1929,20 @@ def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>; // v9.4a Exception-based event profiling (FEAT_EBEP) // Op0 Op1 CRn CRm Op2 def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>; + +// 2023 ISA Extension +// AArch64 Floating-point Mode Register controls behaviors of the FP8 +// instructions (FEAT_FPMR) +let Requires = [{ {AArch64::FeatureFPMR} }] in { +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>; +def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>; +} + +// v9.5a Software Stepping Enhancements (FEAT_STEP2) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>; + +// v9.5a System PMU zero register (FEAT_SPMU2) +// Op0 Op1 CRn CRm Op2 +def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>; |