diff options
Diffstat (limited to 'contrib/binutils/bfd/doc/archures.texi')
| -rw-r--r-- | contrib/binutils/bfd/doc/archures.texi | 67 |
1 files changed, 59 insertions, 8 deletions
diff --git a/contrib/binutils/bfd/doc/archures.texi b/contrib/binutils/bfd/doc/archures.texi index 06ee6d318cee..bf72179dad31 100644 --- a/contrib/binutils/bfd/doc/archures.texi +++ b/contrib/binutils/bfd/doc/archures.texi @@ -46,11 +46,22 @@ enum bfd_architecture #define bfd_mach_m68040 6 #define bfd_mach_m68060 7 #define bfd_mach_cpu32 8 -#define bfd_mach_mcf5200 9 -#define bfd_mach_mcf5206e 10 -#define bfd_mach_mcf5307 11 -#define bfd_mach_mcf5407 12 -#define bfd_mach_mcf528x 13 +#define bfd_mach_mcf_isa_a_nodiv 9 +#define bfd_mach_mcf_isa_a 10 +#define bfd_mach_mcf_isa_a_mac 11 +#define bfd_mach_mcf_isa_a_emac 12 +#define bfd_mach_mcf_isa_aplus 13 +#define bfd_mach_mcf_isa_aplus_mac 14 +#define bfd_mach_mcf_isa_aplus_emac 15 +#define bfd_mach_mcf_isa_b_nousp 16 +#define bfd_mach_mcf_isa_b_nousp_mac 17 +#define bfd_mach_mcf_isa_b_nousp_emac 18 +#define bfd_mach_mcf_isa_b 19 +#define bfd_mach_mcf_isa_b_mac 20 +#define bfd_mach_mcf_isa_b_emac 21 +#define bfd_mach_mcf_isa_b_float 22 +#define bfd_mach_mcf_isa_b_float_mac 23 +#define bfd_mach_mcf_isa_b_float_emac 24 bfd_arch_vax, /* DEC Vax */ bfd_arch_i960, /* Intel 960 */ /* The order of the following is important. @@ -72,7 +83,6 @@ enum bfd_architecture bfd_arch_or32, /* OpenRISC 32 */ - bfd_arch_a29k, /* AMD 29000 */ bfd_arch_sparc, /* SPARC */ #define bfd_mach_sparc 1 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */ @@ -89,6 +99,9 @@ enum bfd_architecture #define bfd_mach_sparc_v9_p(mach) \ ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \ && (mach) != bfd_mach_sparc_sparclite_le) +/* Nonzero if MACH is a 64 bit sparc architecture. */ +#define bfd_mach_sparc_64bit_p(mach) \ + ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb) bfd_arch_mips, /* MIPS Rxxxx */ #define bfd_mach_mips3000 3000 #define bfd_mach_mips3900 3900 @@ -107,6 +120,7 @@ enum bfd_architecture #define bfd_mach_mips6000 6000 #define bfd_mach_mips7000 7000 #define bfd_mach_mips8000 8000 +#define bfd_mach_mips9000 9000 #define bfd_mach_mips10000 10000 #define bfd_mach_mips12000 12000 #define bfd_mach_mips16 16 @@ -127,7 +141,6 @@ enum bfd_architecture bfd_arch_i860, /* Intel 860 */ bfd_arch_i370, /* IBM 360/370 Mainframes */ bfd_arch_romp, /* IBM ROMP PC/RT */ - bfd_arch_alliant, /* Alliant */ bfd_arch_convex, /* Convex */ bfd_arch_m88k, /* Motorola 88xxx */ bfd_arch_m98k, /* Motorola 98xxx */ @@ -190,12 +203,20 @@ enum bfd_architecture #define bfd_mach_sh 1 #define bfd_mach_sh2 0x20 #define bfd_mach_sh_dsp 0x2d +#define bfd_mach_sh2a 0x2a +#define bfd_mach_sh2a_nofpu 0x2b +#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 +#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 +#define bfd_mach_sh2a_or_sh4 0x2a3 +#define bfd_mach_sh2a_or_sh3e 0x2a4 #define bfd_mach_sh2e 0x2e #define bfd_mach_sh3 0x30 +#define bfd_mach_sh3_nommu 0x31 #define bfd_mach_sh3_dsp 0x3d #define bfd_mach_sh3e 0x3e #define bfd_mach_sh4 0x40 #define bfd_mach_sh4_nofpu 0x41 +#define bfd_mach_sh4_nommu_nofpu 0x42 #define bfd_mach_sh4a 0x4a #define bfd_mach_sh4a_nofpu 0x4b #define bfd_mach_sh4al_dsp 0x4d @@ -235,6 +256,9 @@ enum bfd_architecture #define bfd_mach_arc_6 6 #define bfd_mach_arc_7 7 #define bfd_mach_arc_8 8 + bfd_arch_m32c, /* Renesas M16C/M32C. */ +#define bfd_mach_m16c 0x75 +#define bfd_mach_m32c 0x78 bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */ #define bfd_mach_m32r 1 /* For backwards compatibility. */ #define bfd_mach_m32rx 'x' @@ -251,6 +275,7 @@ enum bfd_architecture #define bfd_mach_frvsimple 2 #define bfd_mach_fr300 300 #define bfd_mach_fr400 400 +#define bfd_mach_fr450 450 #define bfd_mach_frvtomcat 499 /* fr500 prototype */ #define bfd_mach_fr500 500 #define bfd_mach_fr550 550 @@ -264,6 +289,10 @@ enum bfd_architecture bfd_arch_iq2000, /* Vitesse IQ2000. */ #define bfd_mach_iq2000 1 #define bfd_mach_iq10 2 + bfd_arch_mt, +#define bfd_mach_ms1 1 +#define bfd_mach_mrisc2 2 +#define bfd_mach_ms2 3 bfd_arch_pj, bfd_arch_avr, /* Atmel AVR microcontrollers. */ #define bfd_mach_avr1 1 @@ -271,7 +300,16 @@ enum bfd_architecture #define bfd_mach_avr3 3 #define bfd_mach_avr4 4 #define bfd_mach_avr5 5 + bfd_arch_bfin, /* ADI Blackfin */ +#define bfd_mach_bfin 1 + bfd_arch_cr16c, /* National Semiconductor CompactRISC. */ +#define bfd_mach_cr16c 1 + bfd_arch_crx, /* National Semiconductor CRX. */ +#define bfd_mach_crx 1 bfd_arch_cris, /* Axis CRIS */ +#define bfd_mach_cris_v0_v10 255 +#define bfd_mach_cris_v32 32 +#define bfd_mach_cris_v10_v32 1032 bfd_arch_s390, /* IBM s390 */ #define bfd_mach_s390_31 31 #define bfd_mach_s390_64 64 @@ -286,7 +324,8 @@ enum bfd_architecture #define bfd_mach_msp13 13 #define bfd_mach_msp14 14 #define bfd_mach_msp15 15 -#define bfd_mach_msp16 16 +#define bfd_mach_msp16 16 +#define bfd_mach_msp21 21 #define bfd_mach_msp31 31 #define bfd_mach_msp32 32 #define bfd_mach_msp33 33 @@ -294,8 +333,20 @@ enum bfd_architecture #define bfd_mach_msp42 42 #define bfd_mach_msp43 43 #define bfd_mach_msp44 44 + bfd_arch_xc16x, /* Infineon's XC16X Series. */ +#define bfd_mach_xc16x 1 +#define bfd_mach_xc16xl 2 +#define bfd_mach_xc16xs 3 bfd_arch_xtensa, /* Tensilica's Xtensa cores. */ #define bfd_mach_xtensa 1 + bfd_arch_maxq, /* Dallas MAXQ 10/20 */ +#define bfd_mach_maxq10 10 +#define bfd_mach_maxq20 20 + bfd_arch_z80, +#define bfd_mach_z80strict 1 /* No undocumented opcodes. */ +#define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */ +#define bfd_mach_z80full 7 /* All undocumented instructions. */ +#define bfd_mach_r800 11 /* R800: successor with multiplication. */ bfd_arch_last @}; @end example |