diff options
35 files changed, 2364 insertions, 91 deletions
diff --git a/sys/alpha/alpha/autoconf.c b/sys/alpha/alpha/autoconf.c index 6456d7de6472..35372c3d23c3 100644 --- a/sys/alpha/alpha/autoconf.c +++ b/sys/alpha/alpha/autoconf.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: autoconf.c,v 1.4 1998/07/12 16:07:05 dfr Exp $ + * $Id: autoconf.c,v 1.5 1998/07/22 08:34:19 dfr Exp $ */ #include <sys/param.h> @@ -107,10 +107,15 @@ configure(void *dummy) void cpu_rootconf() { + static char rootname[] = "sd0a"; mountrootfsname = "ufs"; - rootdevs[0] = makedev(4, dkmakeminor(0, COMPATIBILITY_SLICE, 0)); - rootdevs[1] = makedev(4, dkmakeminor(1, COMPATIBILITY_SLICE, 0)); - rootdevnames[0] = "sd0a"; + + rootdevs[0] = rootdev; + rootname[2] += dkunit(rootdev); + rootdevnames[0] = rootname; + + rootdevs[1] = makedev(4, dkmakeminor(0, COMPATIBILITY_SLICE, 0)); + rootdevnames[1] = "sd0a"; } void diff --git a/sys/alpha/alpha/cpuconf.c b/sys/alpha/alpha/cpuconf.c index 9e395ae37145..887a542d11b0 100644 --- a/sys/alpha/alpha/cpuconf.c +++ b/sys/alpha/alpha/cpuconf.c @@ -1,4 +1,4 @@ -/* $Id$ */ +/* $Id: cpuconf.c,v 1.1 1998/06/10 10:52:18 dfr Exp $ */ /* $NetBSD: cpuconf.c,v 1.10 1998/03/20 21:48:21 thorpej Exp $ */ /* @@ -93,6 +93,12 @@ extern void avalon_a12_init __P((int)); #define avalon_a12_init platform_not_configured #endif +#ifdef DEC_ST550 +extern void st550_init __P((int)); +#else +#define st550_init platform_not_configured +#endif + struct cpuinit cpuinit[] = { cpu_notsupp("???"), /* 0: ??? */ cpu_notsupp("ST_ADU"), /* 1: ST_ADU */ @@ -124,7 +130,7 @@ struct cpuinit cpuinit[] = { cpu_notsupp("ST_DEC_1000A"), /* 27: ST_DEC_1000A */ cpu_notsupp("ST_DEC_ALPHAVME_224"), /* 28: ST_DEC_ALPHAVME_224 */ cpu_notsupp("???"), /* 29: ??? */ - cpu_notsupp("???"), /* 30: ??? */ + cpu_init(st550_init,"DEC_ST550"), /* 30: ST_DEC_550 */ cpu_notsupp("???"), /* 31: ??? */ cpu_notsupp("ST_DEC_EV56_PBP"), /* 32: ST_DEC_EV56_PBP */ cpu_notsupp("ST_DEC_ALPHAVME_320"), /* 33: ST_DEC_ALPHAVME_320 */ @@ -154,7 +160,7 @@ platform_not_supported(int cputype) typestr = cpuinit[cputype].option; printf("\n"); - printf("NetBSD does not yet support system type %d (%s).\n", cputype, + printf("FreeBSD does not yet support system type %d (%s).\n", cputype, typestr); printf("\n"); panic("platform not supported"); diff --git a/sys/alpha/alpha/dec_2100_a50.c b/sys/alpha/alpha/dec_2100_a50.c new file mode 100644 index 000000000000..f7bb8c7841ec --- /dev/null +++ b/sys/alpha/alpha/dec_2100_a50.c @@ -0,0 +1,252 @@ +/* $NetBSD: dec_2100_a50.c,v 1.39 1998/04/17 02:45:19 mjacob Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/termios.h> + +#include <machine/rpb.h> +#include <machine/cpuconf.h> +#include <machine/clock.h> +#include <pci/pcireg.h> +#include <pci/pcivar.h> +#include <pci/pci_ioctl.h> +#include <alpha/pci/apecsreg.h> +#include <alpha/pci/apecsvar.h> + +#include "sio.h" +#include "sc.h" +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void dec_2100_a50_init __P((void)); +static void dec_2100_a50_cons_init __P((void)); +static void dec_2100_a50_device_register __P((struct device *, void *)); +static void dec_2100_a50_intr_map __P((void *)); +void sio_intr_establish __P((int)); +void sio_intr_disestablish __P((int)); +void sio_intr_setup __P((void)); + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +const struct alpha_variation_table dec_2100_a50_variations[] = { + { SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" }, + { SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" }, + { SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" }, + { SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" }, + { SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" }, + { SV_ST_AVANTI_4_233, "AlphaStation 255/233" }, + { 0, NULL }, +}; + +void +dec_2100_a50_init() +{ + u_int64_t variation; + + platform.family = "AlphaStation 200/400 (\"Avanti\")"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + variation = hwrpb->rpb_variation & SV_ST_MASK; + if (variation == SV_ST_AVANTI_XXX) { + /* XXX apparently the same? */ + variation = SV_ST_AVANTI; + } + if ((platform.model = alpha_variation_name(variation, + dec_2100_a50_variations)) == NULL) + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "apecs"; + platform.cons_init = dec_2100_a50_cons_init; + platform.pci_intr_map = dec_2100_a50_intr_map; +} + +extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */ + +static void +dec_2100_a50_cons_init() +{ + struct ctb *ctb; + + apecs_init(); + +#ifdef DDB + siogdbattach(0x2f8, 9600); +#endif + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + /* + * force a comconsole on com1 if the SRM has a serial console + */ + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */ + +void +dec_2100_a50_intr_map(void *arg) +{ + u_int8_t pirqline; + u_int32_t pirqreg; + int pirq=0; /* gcc -Wuninitialized XXX */ + pcicfgregs *cfg = (pcicfgregs *)arg; + static int intr_setup_done=0; + + /* + * Slot->interrupt translation. Taken from NetBSD + */ + + if(cfg->intpin == 0) + return; + + if(cfg->intpin > 4) + panic("dec_2100_a50_intr_map: bad intpin %d",cfg->intpin); + + switch (cfg->slot) { + case 6: /* NCR SCSI */ + pirq = 3; + break; + + case 11: /* slot 1 */ + case 14: /* slot 3 */ + switch(cfg->intpin){ + case 1: + case 4: + pirq = 0; + break; + case 2: + pirq = 2; + break; + case 3: + pirq = 1; + break; + default: + panic("dec_2100_a50_intr_map bogus PCI pin %d\n", + cfg->intpin); + + } + break; + case 12: /* slot 2 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 1; + break; + case 2: + pirq = 0; + break; + case 3: + pirq = 2; + break; + default: + panic("dec_2100_a50_intr_map bogus PCI pin %d\n", + cfg->intpin); + + }; + break; + + case 13: /* slot 3 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 2; + break; + case 2: + pirq = 1; + break; + case 3: + pirq = 0; + break; + }; + break; + default: + printf("dec_2100_a50_intr_map: weird slot %d\n", + cfg->slot); +/* return;*/ + } + + /* + * read the SIO IRQ routing register to determine where the + * interrupt will actually be routed. Thank you, NetBSD + */ + + pirqreg = chipset.cfgreadl(0, 7, 0, SIO_PCIREG_PIRQ_RTCTRL); + pirqline = (pirqreg >> (pirq * 8)) & 0xff; + if ((pirqline & 0x80) != 0) + panic("bad pirqline %d",pirqline); + pirqline &= 0xf; + cfg->intline = pirqline; +} diff --git a/sys/alpha/alpha/dec_axppci_33.c b/sys/alpha/alpha/dec_axppci_33.c new file mode 100644 index 000000000000..5245de546e2a --- /dev/null +++ b/sys/alpha/alpha/dec_axppci_33.c @@ -0,0 +1,282 @@ +/* $Id$ */ +/* $NetBSD: dec_axppci_33.c,v 1.38 1998/07/07 08:49:12 ross Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/termios.h> + +#include <machine/rpb.h> +#include <machine/cpuconf.h> +#include <machine/clock.h> +#include <pci/pcireg.h> +#include <pci/pcivar.h> +#include <pci/pci_ioctl.h> +#include <alpha/pci/lcavar.h> + +#include "sio.h" +#include "sc.h" +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void dec_axppci_33_init __P((void)); +static void dec_axppci_33_cons_init __P((void)); +static void dec_axppci_33_intr_map __P((void *)); + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +const struct alpha_variation_table dec_axppci_33_variations[] = { + { 0, "Alpha PC AXPpci33 (\"NoName\")" }, + { 0, NULL }, +}; + +#define NSIO_PORT 0x26e /* Hardware enabled option: 0x398 */ +#define NSIO_BASE 0 +#define NSIO_INDEX NSIO_BASE +#define NSIO_DATA 1 +#define NSIO_SIZE 2 +#define NSIO_CFG0 0 +#define NSIO_CFG1 1 +#define NSIO_CFG2 2 +#define NSIO_IDE_ENABLE 0x40 + +void +dec_axppci_33_init() +{ + int cfg0val; + u_int64_t variation; + + platform.family = "DEC AXPpci"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + variation = hwrpb->rpb_variation & SV_ST_MASK; + if ((platform.model = alpha_variation_name(variation, + dec_axppci_33_variations)) == NULL) + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "lca"; + platform.cons_init = dec_axppci_33_cons_init; + platform.pci_intr_map = dec_axppci_33_intr_map; + + lca_init(); + + outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0); + alpha_mb(); + cfg0val = inb(NSIO_PORT + NSIO_DATA); + + cfg0val |= NSIO_IDE_ENABLE; + + outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0); + alpha_mb(); + outb(NSIO_PORT + NSIO_DATA, cfg0val); + alpha_mb(); + outb(NSIO_PORT + NSIO_DATA, cfg0val); +} + +extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */ + +static void +dec_axppci_33_cons_init() +{ + struct ctb *ctb; + struct lca_config *lcp; + + lca_init(); + +#ifdef DDB + siogdbattach(0x2f8, 9600); +#endif + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + /* + * force a comconsole on com1 if the SRM has a serial console + */ + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */ + +void +dec_axppci_33_intr_map(void *arg) +{ + pcicfgregs *cfg = (pcicfgregs *)arg; + int pirq; + u_int32_t pirqreg; + u_int8_t pirqline; + +#ifndef DIAGNOSTIC + pirq = 0; /* XXX gcc -Wuninitialized */ +#endif + + /* + * Slot->interrupt translation. Taken from NetBSD + */ + + if (cfg->intpin == 0) { + /* No IRQ used. */ + return; + } + if (cfg->intpin > 4) { + printf("dec_axppci_33_intr_map: bad interrupt pin %d\n", + cfg->intpin); + return; + } + + switch (cfg->slot) { + case 6: /* NCR SCSI */ + pirq = 3; + break; + + case 11: /* slot 1 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 0; + break; + case 2: + pirq = 2; + break; + case 3: + pirq = 1; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map: bogus PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + case 12: /* slot 2 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 1; + break; + case 2: + pirq = 0; + break; + case 3: + pirq = 2; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map: bogus PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + case 8: /* slot 3 */ + switch (cfg->intpin) { + case 1: + case 4: + pirq = 2; + break; + case 2: + pirq = 1; + break; + case 3: + pirq = 0; + break; +#ifdef DIAGNOSTIC + default: /* XXX gcc -Wuninitialized */ + panic("dec_axppci_33_intr_map bogus: PCI pin %d\n", + cfg->intpin); +#endif + }; + break; + + default: + printf("dec_axppci_33_intr_map: weird device number %d\n", + cfg->slot); + return; + } + + pirqreg = chipset.cfgreadl(0, 7, 0, SIO_PCIREG_PIRQ_RTCTRL); +#if 0 + printf("dec_axppci_33_intr_map: device %d pin %c: pirq %d, reg = %x\n", + device, '@' + cfg->intpin, pirq, pirqreg); +#endif + pirqline = (pirqreg >> (pirq * 8)) & 0xff; + if ((pirqline & 0x80) != 0) + panic("bad pirqline %d",pirqline); + pirqline &= 0xf; + +#if 0 + printf("dec_axppci_33_intr_map: device %d pin %c: mapped to line %d\n", + device, '@' + cfg->intpin, pirqline); +#endif + + cfg->intline = pirqline; +} diff --git a/sys/alpha/alpha/dec_eb164.c b/sys/alpha/alpha/dec_eb164.c index 72a1dd8bc43b..c0553878288b 100644 --- a/sys/alpha/alpha/dec_eb164.c +++ b/sys/alpha/alpha/dec_eb164.c @@ -1,4 +1,4 @@ -/* $Id: dec_eb164.c,v 1.2 1998/07/12 16:07:43 dfr Exp $ */ +/* $Id: dec_eb164.c,v 1.3 1998/07/22 08:18:34 dfr Exp $ */ /* $NetBSD: dec_eb164.c,v 1.26 1998/04/17 02:45:19 mjacob Exp $ */ /* @@ -42,6 +42,8 @@ #include <machine/cpuconf.h> #include <machine/clock.h> +#include <alpha/pci/ciavar.h> + #include "sio.h" #include "sc.h" @@ -52,9 +54,14 @@ static int comcnrate = CONSPEED; void dec_eb164_init __P((void)); static void dec_eb164_cons_init __P((void)); +static void eb164_intr_init(void); extern void eb164_intr_enable(int irq); extern void eb164_intr_disable(int irq); +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + void dec_eb164_init() { @@ -67,6 +74,7 @@ dec_eb164_init() platform.iobus = "cia"; platform.cons_init = dec_eb164_cons_init; + platform.pci_intr_init = eb164_intr_init; platform.pci_intr_map = NULL; platform.pci_intr_disable = eb164_intr_disable; platform.pci_intr_enable = eb164_intr_enable; @@ -121,3 +129,12 @@ dec_eb164_cons_init() ctb->ctb_term_type); } } + +static void +eb164_intr_init() +{ + /* + * Enable ISA-PCI cascade interrupt. + */ + eb164_intr_enable(4); +} diff --git a/sys/alpha/alpha/dec_kn20aa.c b/sys/alpha/alpha/dec_kn20aa.c index 11f84042d761..2f018fb20691 100644 --- a/sys/alpha/alpha/dec_kn20aa.c +++ b/sys/alpha/alpha/dec_kn20aa.c @@ -44,6 +44,7 @@ #include <pci/pcivar.h> #include <pci/pci_ioctl.h> #include <alpha/pci/ciareg.h> +#include <alpha/pci/ciavar.h> #include "sio.h" #include "sc.h" @@ -55,10 +56,15 @@ static int comcnrate = CONSPEED; void dec_kn20aa_init __P((void)); static void dec_kn20aa_cons_init __P((void)); +static void dec_kn20aa_intr_init __P((void)); static void dec_kn20aa_intr_map __P((void *)); static void dec_kn20aa_intr_disable __P((int)); static void dec_kn20aa_intr_enable __P((int)); +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + #if 0 static void dec_kn20aa_device_register __P((struct device *, void *)); #endif @@ -85,6 +91,7 @@ dec_kn20aa_init() platform.iobus = "cia"; platform.cons_init = dec_kn20aa_cons_init; + platform.pci_intr_init = dec_kn20aa_intr_init; platform.pci_intr_map = dec_kn20aa_intr_map; platform.pci_intr_disable = dec_kn20aa_intr_disable; platform.pci_intr_enable = dec_kn20aa_intr_enable; @@ -259,6 +266,15 @@ dec_kn20aa_device_register(dev, aux) #define KN20AA_MAX_IRQ 32 void +dec_kn20aa_intr_init() +{ + /* + * Enable ISA-PCI cascade interrupt. + */ + dec_kn20aa_intr_enable(31); +} + +void dec_kn20aa_intr_map(void *arg) { pcicfgregs *cfg = (pcicfgregs *)arg; diff --git a/sys/alpha/alpha/dec_st550.c b/sys/alpha/alpha/dec_st550.c new file mode 100644 index 000000000000..758b611907cb --- /dev/null +++ b/sys/alpha/alpha/dec_st550.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <machine/intr.h> + +#include <sys/device.h> +#include <sys/termios.h> + +#include <machine/rpb.h> +#include <machine/cpuconf.h> +#include <machine/clock.h> +#include <pci/pcireg.h> +#include <pci/pcivar.h> +#include <pci/pci_ioctl.h> +#include <alpha/pci/ciareg.h> +#include <alpha/pci/ciavar.h> + +#include "sio.h" +#include "sc.h" + +#ifndef CONSPEED +#define CONSPEED TTYDEF_SPEED +#endif +static int comcnrate = CONSPEED; + +void st550_init __P((void)); +static void st550_cons_init __P((void)); +static void st550_intr_init __P((void)); +static void pyxis_intr_enable __P((int)); +static void pyxis_intr_disable __P((int)); +static void st550_intr_enable __P((int)); +static void st550_intr_disable __P((int)); +static void st550_intr_map __P((void *)); +#define ST550_PCI_IRQ_BEGIN 8 +#define ST550_PCI_MAX_IRQ 47 + +extern int siocnattach __P((int, int)); +extern int siogdbattach __P((int, int)); +extern int sccnattach __P((void)); + +void +st550_init() +{ + int i; + platform.family = "Digital Personal Workstation (Miata)"; + + if ((platform.model = alpha_dsr_sysname()) == NULL) { + /* XXX Don't know the system variations, yet. */ + platform.model = alpha_unknown_sysname(); + } + + platform.iobus = "cia"; + platform.cons_init = st550_cons_init; + platform.pci_intr_init = st550_intr_init; + platform.pci_intr_map = st550_intr_map; + platform.pci_intr_disable = st550_intr_disable; + platform.pci_intr_enable = st550_intr_enable; +} + +extern int comconsole; + +static void +st550_cons_init() +{ + struct ctb *ctb; + + cia_init(); + +#ifdef DDB + siogdbattach(0x2f8, 57600); +#endif + + ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off); + + switch (ctb->ctb_term_type) { + case 2: + /* serial console ... */ + /* XXX */ + { + /* + * Delay to allow PROM putchars to complete. + * FIFO depth * character time, + * character time = (1000000 / (defaultrate / 10)) + */ + DELAY(160000000 / comcnrate); + comconsole = 0; + if (siocnattach(0x3f8, comcnrate)) + panic("can't init serial console"); + + break; + } + + case 3: + /* display console ... */ + /* XXX */ +#if NSC > 0 + sccnattach(); +#else + panic("not configured to use display && keyboard console"); +#endif + break; + + default: + printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type); + printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot); + + panic("consinit: unknown console type %d\n", + ctb->ctb_term_type); + } +} + +static void +st550_intr_init() +{ + /* This is here because we need to disable extraneous pci interrupts. */ + int i; + for(i = ST550_PCI_IRQ_BEGIN; i <= ST550_PCI_MAX_IRQ; i++) + pyxis_intr_disable(i); + /* From Linux... */ + pyxis_intr_enable(2); /* enable HALT switch */ + pyxis_intr_enable(6); /* enable timer */ + pyxis_intr_enable(7); /* enable ISA PIC cascade */ +} + +static void +st550_intr_map(void *arg) +{ + pcicfgregs *cfg = (pcicfgregs *)arg; + + /* There are two main variants of Miata: Miata 1 (Intel SIO) + * and Miata {1.5,2} (Cypress). + * + * The Miata 1 has a CMD PCI IDE wired to compatibility mode at + * slot 4 of bus 0. This variant has the Pyxis DMA bug. + * + * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives + * on device 7 of bus 0. This device has PCI IDE wired to + * compatibility mode on functions 1 and 2. + * + * There will be no interrupt mapping for these devices, so just + * bail out now. + */ + if(cfg->bus == 0) { + if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { + /* Miata 1 */ + if (cfg->slot == 7) + return; + else if (cfg->func == 4) + return; + } else { + /* Miata 1.5 or Miata 2 */ + if (cfg->slot == 7) { + if (cfg->func == 0) + return; + return; + } + } + } + /* Account for the PCI interrupt offset. */ + /* cfg->intline += ST550_PCI_IRQ_BEGIN; */ + return; +} + +/* + * The functions below were written based on a draft copy of the + * 21174 TRM. + */ +static void +pyxis_intr_enable(irq) + int irq; +{ + volatile u_int64_t temp; + + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); + alpha_mb(); + + temp |= ( 1L << irq ); + REGVAL64(PYXIS_INT_MASK) = temp; + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); +#ifdef 0 + printf("pyxis_intr_enable: enabling %d, current mask= ", irq); + { + int i; + for ( i = 0; i < 61; i++) + if (temp & (1 << i)){ + printf("%d " ,i); + } + printf("\n"); + } +#endif + +} + +static void +pyxis_intr_disable(irq) + int irq; +{ + volatile u_int64_t temp; + + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); + temp &= ~(1L << irq ); + REGVAL64(PYXIS_INT_MASK) = temp; + alpha_mb(); + temp = REGVAL64(PYXIS_INT_MASK); +#if 0 + printf("pyxis_intr_disable: disabled %d, current mask ", irq); + { + int i; + for ( i = 0; i < 61; i++) + if (temp & (1 << i)){ + printf("%d ",i); + } + printf("\n"); + } +#endif + +} + +static void +st550_intr_enable(irq) + int irq; +{ + pyxis_intr_enable(irq + ST550_PCI_IRQ_BEGIN); +} + +static void +st550_intr_disable(irq) + int irq; +{ + pyxis_intr_disable(irq + ST550_PCI_IRQ_BEGIN); +} diff --git a/sys/alpha/alpha/interrupt.c b/sys/alpha/alpha/interrupt.c index 202e17984e2f..9390f8fb6b68 100644 --- a/sys/alpha/alpha/interrupt.c +++ b/sys/alpha/alpha/interrupt.c @@ -1,4 +1,4 @@ -/* $Id: interrupt.c,v 1.3 1998/07/05 12:22:56 dfr Exp $ */ +/* $Id: interrupt.c,v 1.4 1998/07/12 16:09:27 dfr Exp $ */ /* $NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $ */ /* @@ -71,7 +71,7 @@ interrupt(a0, a1, a2, framep) struct proc* p = curproc; if (!p) p = &proc0; if ((caddr_t) framep < (caddr_t) p->p_addr + 1024) - printf("possible stack overflow\n"); + panic("possible stack overflow\n"); } switch (a0) { @@ -307,7 +307,7 @@ alpha_connect_intr(struct alpha_intr *i) } void -alpha_dispatch_intr(int vector) +alpha_dispatch_intr(void *frame, unsigned long vector) { struct alpha_intr *i; int h = HASHVEC(vector); diff --git a/sys/alpha/alpha/locore.s b/sys/alpha/alpha/locore.s index 48f78c3f5cdb..1a97de23c531 100644 --- a/sys/alpha/alpha/locore.s +++ b/sys/alpha/alpha/locore.s @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: locore.s,v 1.1 1998/06/10 10:52:50 dfr Exp $ + * $Id: locore.s,v 1.2 1998/06/10 19:59:40 dfr Exp $ */ /* * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. @@ -78,8 +78,6 @@ call_pal PAL_OSF1_swpctx .text - EXPORT(kernel_text) -kernel_text: NESTED(locorestart, 1, 0, ra, 0, 0) diff --git a/sys/alpha/alpha/machdep.c b/sys/alpha/alpha/machdep.c index 66948c0fc829..ea7eb6fa2876 100644 --- a/sys/alpha/alpha/machdep.c +++ b/sys/alpha/alpha/machdep.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: machdep.c,v 1.9 1998/07/29 18:36:29 dfr Exp $ + * $Id: machdep.c,v 1.10 1998/07/30 08:10:26 dfr Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -1801,3 +1801,19 @@ bad: return(-1); } + +void atomic_add(u_int32_t* p, u_int32_t v) +{ + u_int32_t temp; + __asm__ __volatile__ ( + "1:\tldl_l %0,%2\n\t" /* load counter value, asserting lock */ + "addl %3,%0,%0\n\t" /* add our bits */ + "stl_c %0,%1\n\t" /* attempt to store */ + "beq %0,2f\n\t" /* if the store failed, spin */ + "br 3f\n" /* it worked, exit */ + "2:\tbr 1b\n" /* *p not updated, loop */ + "3:\tmb\n" /* it worked */ + : "=&r"(temp), "=m" (*p) + : "m"(*p), "r"(v) + : "memory"); +} diff --git a/sys/alpha/conf/GENERIC b/sys/alpha/conf/GENERIC index a5c74c855665..3265a1b6bad6 100644 --- a/sys/alpha/conf/GENERIC +++ b/sys/alpha/conf/GENERIC @@ -11,16 +11,20 @@ # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.1 1998/06/10 10:53:56 dfr Exp $ +# $Id: GENERIC,v 1.2 1998/08/07 08:16:31 dfr Exp $ machine "alpha" +cpu "EV4" cpu "EV5" ident GENERIC maxusers 10 # Platforms supported +options "DEC_AXPPCI_33" # UDB, Multia, AXPpci33, Noname options "DEC_EB164" # EB164, PC164, PC164LX, PC164SX +options "DEC_2100_A50" # AlphaStation 200, 250, 255, 400 options "DEC_KN20AA" # AlphaStation 500, 600 +options "DEC_ST550" # Personal Workstation 433, 500, 600 options INET #InterNETworking options FFS #Berkeley Fast Filesystem @@ -40,6 +44,8 @@ config kernel root on sd0 # Platform chipsets controller cia0 +controller apecs0 +controller lca0 # Standard busses controller pci0 diff --git a/sys/alpha/conf/Makefile.alpha b/sys/alpha/conf/Makefile.alpha index c98b3d7e2a38..290b24ce4df5 100644 --- a/sys/alpha/conf/Makefile.alpha +++ b/sys/alpha/conf/Makefile.alpha @@ -1,7 +1,7 @@ # Makefile.alpha -- with config changes. # Copyright 1990 W. Jolitz # from: @(#)Makefile.alpha 7.1 5/10/91 -# $Id: Makefile.alpha,v 1.5 1998/07/22 08:23:26 dfr Exp $ +# $Id: Makefile.alpha,v 1.6 1998/07/30 08:12:14 dfr Exp $ # # Makefile for FreeBSD # @@ -79,7 +79,7 @@ SYSTEM_LD_HEAD= @echo loading $@; rm -f $@ .if ${BINFORMAT} == elf SYSTEM_OBJS= locore.o setdef0.o vnode_if.o \ ${OBJS} ioconf.o param.o config.o \ - setdef1.o + setdef1.o hack.so SYSTEM_LD= @${LD} --export-dynamic -T$S/alpha/conf/kernel.script -e locorestart \ -o $@ -X ${SYSTEM_OBJS} vers.o SYSTEM_LD_TAIL= @${SIZE} $@; chmod 755 $@ @@ -119,6 +119,11 @@ symbols.sort: ${ALPHA}/alpha/symbols.raw locore.o: ${ALPHA}/alpha/locore.s assym.s ${NORMAL_S} +hack.so: Makefile + echo "void __elf_kld_hack() {}" > hack.c + ${CC} -shared -nostdlib hack.c -o hack.so + rm -f hack.c + setdef0.o: ${ALPHA}/alpha/setdef0.c setdefs.h ${NORMAL_C} diff --git a/sys/alpha/conf/NOTES b/sys/alpha/conf/NOTES index a5c74c855665..3265a1b6bad6 100644 --- a/sys/alpha/conf/NOTES +++ b/sys/alpha/conf/NOTES @@ -11,16 +11,20 @@ # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.1 1998/06/10 10:53:56 dfr Exp $ +# $Id: GENERIC,v 1.2 1998/08/07 08:16:31 dfr Exp $ machine "alpha" +cpu "EV4" cpu "EV5" ident GENERIC maxusers 10 # Platforms supported +options "DEC_AXPPCI_33" # UDB, Multia, AXPpci33, Noname options "DEC_EB164" # EB164, PC164, PC164LX, PC164SX +options "DEC_2100_A50" # AlphaStation 200, 250, 255, 400 options "DEC_KN20AA" # AlphaStation 500, 600 +options "DEC_ST550" # Personal Workstation 433, 500, 600 options INET #InterNETworking options FFS #Berkeley Fast Filesystem @@ -40,6 +44,8 @@ config kernel root on sd0 # Platform chipsets controller cia0 +controller apecs0 +controller lca0 # Standard busses controller pci0 diff --git a/sys/alpha/conf/files.alpha b/sys/alpha/conf/files.alpha index 396d707fb354..5e28c2c43f2d 100644 --- a/sys/alpha/conf/files.alpha +++ b/sys/alpha/conf/files.alpha @@ -1,7 +1,7 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # -# $Id: files.alpha,v 1.3 1998/07/12 16:26:52 dfr Exp $ +# $Id: files.alpha,v 1.4 1998/07/22 08:24:39 dfr Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and @@ -19,6 +19,9 @@ alpha/alpha/cpuconf.c standard alpha/alpha/dec_kn8ae.c optional dec_kn8ae alpha/alpha/dec_eb164.c optional dec_eb164 alpha/alpha/dec_kn20aa.c optional dec_kn20aa +alpha/alpha/dec_2100_a50.c optional dec_2100_a50 +alpha/alpha/dec_st550.c optional dec_st550 +alpha/alpha/dec_axppci_33.c optional dec_axppci_33 alpha/alpha/mountroot.c optional slice alpha/alpha/ipl_funcs.c standard alpha/alpha/pal.s standard @@ -79,6 +82,8 @@ mcclock_if.h standard \ alpha/pci/cia.c optional cia alpha/pci/pci_eb164_intr.s optional cia alpha/isa/mcclock_isa.c optional cia +alpha/pci/apecs.c optional apecs +alpha/pci/lca.c optional lca alpha/pci/pcibus.c optional pci alpha/isa/isa.c optional isa kern/link_elf.c standard diff --git a/sys/alpha/conf/kernel.script b/sys/alpha/conf/kernel.script index eac78dd31df4..1bcfd9079bb2 100644 --- a/sys/alpha/conf/kernel.script +++ b/sys/alpha/conf/kernel.script @@ -3,8 +3,7 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/sys/alpha/conf/options.alpha b/sys/alpha/conf/options.alpha index f626ca22e569..3132f9ad5bbe 100644 --- a/sys/alpha/conf/options.alpha +++ b/sys/alpha/conf/options.alpha @@ -1,9 +1,12 @@ -# $Id: options.alpha,v 1.2 1998/07/12 16:28:09 dfr Exp $ +# $Id: options.alpha,v 1.3 1998/07/22 08:24:39 dfr Exp $ EV5 opt_global.h DEC_KN8AE opt_cpu.h DEC_EB164 opt_cpu.h DEC_KN20AA opt_cpu.h +DEC_2100_A50 opt_cpu.h +DEC_ST550 opt_cpu.h +DEC_AXPPCI_33 opt_cpu.h ATAPI opt_atapi.h ATAPI_STATIC opt_atapi.h diff --git a/sys/alpha/include/chipset.h b/sys/alpha/include/chipset.h index 772f3e08e3be..5e2922ed728e 100644 --- a/sys/alpha/include/chipset.h +++ b/sys/alpha/include/chipset.h @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: chipset.h,v 1.2 1998/07/12 16:16:22 dfr Exp $ + * $Id: chipset.h,v 1.3 1998/07/22 08:25:39 dfr Exp $ */ #ifndef _MACHINE_CHIPSET_H_ @@ -88,11 +88,11 @@ typedef struct alpha_chipset { alpha_chipset_cfgwritel_t* cfgwritel; /* - * PCI bridge device. + * PCI interrupt device. * (XXX hack until I change pci code to use new * device framework.) */ - void* bridge; + void* intrdev; } alpha_chipset_t; extern alpha_chipset_t chipset; diff --git a/sys/alpha/include/cpuconf.h b/sys/alpha/include/cpuconf.h index c38510cb01a3..6bddc82cf255 100644 --- a/sys/alpha/include/cpuconf.h +++ b/sys/alpha/include/cpuconf.h @@ -69,6 +69,7 @@ extern struct platform { void (*clockintr) __P((void *)); void (*mcheck_handler) __P((unsigned long, struct trapframe *, unsigned long, unsigned long)); + void (*pci_intr_init) __P((void)); void (*pci_intr_map) __P((void *)); void (*pci_intr_disable) __P((int)); void (*pci_intr_enable) __P((int)); diff --git a/sys/alpha/include/intr.h b/sys/alpha/include/intr.h index 9a33081a3c2f..79af6fd9fa6d 100644 --- a/sys/alpha/include/intr.h +++ b/sys/alpha/include/intr.h @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id$ + * $Id: intr.h,v 1.2 1998/07/12 16:09:30 dfr Exp $ */ #ifndef _MACHINE_INTR_H_ @@ -41,6 +41,6 @@ struct alpha_intr { struct alpha_intr *alpha_create_intr(int vector, driver_intr_t *intr, void *arg); int alpha_connect_intr(struct alpha_intr *i); -void alpha_dispatch_intr(int vector); +void alpha_dispatch_intr(void *frame, unsigned long vector); #endif /* !_MACHINE_INTR_H_ */ diff --git a/sys/alpha/include/rpb.h b/sys/alpha/include/rpb.h index 164127ff9721..b5d0892ae192 100644 --- a/sys/alpha/include/rpb.h +++ b/sys/alpha/include/rpb.h @@ -131,6 +131,44 @@ struct rpb { #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */ +#define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */ + +/* + * System types for the AXPvme Family + */ +#define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */ +#define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */ +#define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */ +#define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */ +#define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */ +#define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */ +#define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */ + +/* + * System types for the EB164 Family + */ +#define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */ +#define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */ +#define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */ +#define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */ +#define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */ +#define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */ +#define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */ +#define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */ +#define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */ +#define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */ +#define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */ +#define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */ +#define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */ +#define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */ +#define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */ + +/* + * System types for the Digital Personal Workstation (Miata) Family + * XXX These are not very complete! + */ +#define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */ + u_int64_t rpb_variation; /* 58 */ char rpb_revision[8]; /* 60; only first 4 valid */ diff --git a/sys/alpha/isa/isa.c b/sys/alpha/isa/isa.c index 713fc1ba0eec..e421f71d9539 100644 --- a/sys/alpha/isa/isa.c +++ b/sys/alpha/isa/isa.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: isa.c,v 1.1 1998/07/22 08:29:26 dfr Exp $ + * $Id: isa.c,v 1.2 1998/07/27 09:38:26 dfr Exp $ */ #include <sys/param.h> @@ -274,6 +274,11 @@ struct isa_intr { int irq; }; +/* + * Wrap ISA interrupt routines so that we can feed non-specific + * EOI to the PICs. + */ + static void isa_handle_intr(void *arg) { @@ -300,9 +305,8 @@ isa_create_intr(device_t dev, device_t child, int irq, ii->intr = intr; ii->arg = arg; ii->irq = irq; - ii->ih = BUS_CREATE_INTR(device_get_parent(dev), dev, - 0x800 + (irq << 4), - isa_handle_intr, ii); + ii->ih = alpha_create_intr(0x800 + (irq << 4), isa_handle_intr, ii); + if (!ii->ih) { free(ii, M_DEVBUF); return NULL; @@ -318,7 +322,9 @@ isa_connect_intr(device_t dev, void *ih) struct alpha_intr *i = ii->ih; isa_intr_enable(ii->irq); - return BUS_CONNECT_INTR(device_get_parent(dev), ii->ih); + return alpha_connect_intr(i); } DRIVER_MODULE(isa, cia, isa_driver, isa_devclass, 0, 0); +DRIVER_MODULE(isa, apecs, isa_driver, isa_devclass, 0, 0); +DRIVER_MODULE(isa, lca, isa_driver, isa_devclass, 0, 0); diff --git a/sys/alpha/pci/apecs.c b/sys/alpha/pci/apecs.c new file mode 100644 index 000000000000..4043fd397085 --- /dev/null +++ b/sys/alpha/pci/apecs.c @@ -0,0 +1,488 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: cia.c,v 1.3 1998/07/22 08:32:17 dfr Exp $ + */ +/* + * Copyright (c) 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/bus.h> + +#include <alpha/pci/apecsreg.h> +#include <alpha/pci/apecsvar.h> +#include <machine/intr.h> +#include <machine/cpuconf.h> +#include <machine/swiz.h> + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t apecs_devclass; +static device_t apecs0; /* XXX only one for now */ +static device_t isa0; + +struct apecs_softc { + vm_offset_t dmem_base; /* dense memory */ + vm_offset_t smem_base; /* sparse memory */ + vm_offset_t io_base; /* dense i/o */ + vm_offset_t cfg0_base; /* dense pci0 config */ + vm_offset_t cfg1_base; /* dense pci1 config */ +}; + +#define APECS_SOFTC(dev) (struct apecs_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t apecs_swiz_inb; +static alpha_chipset_inw_t apecs_swiz_inw; +static alpha_chipset_inl_t apecs_swiz_inl; +static alpha_chipset_outb_t apecs_swiz_outb; +static alpha_chipset_outw_t apecs_swiz_outw; +static alpha_chipset_outl_t apecs_swiz_outl; +static alpha_chipset_readb_t apecs_swiz_readb; +static alpha_chipset_readw_t apecs_swiz_readw; +static alpha_chipset_readl_t apecs_swiz_readl; +static alpha_chipset_writeb_t apecs_swiz_writeb; +static alpha_chipset_writew_t apecs_swiz_writew; +static alpha_chipset_writel_t apecs_swiz_writel; +static alpha_chipset_maxdevs_t apecs_swiz_maxdevs; +static alpha_chipset_cfgreadb_t apecs_swiz_cfgreadb; +static alpha_chipset_cfgreadw_t apecs_swiz_cfgreadw; +static alpha_chipset_cfgreadl_t apecs_swiz_cfgreadl; +static alpha_chipset_cfgwriteb_t apecs_swiz_cfgwriteb; +static alpha_chipset_cfgwritew_t apecs_swiz_cfgwritew; +static alpha_chipset_cfgwritel_t apecs_swiz_cfgwritel; + +static alpha_chipset_t apecs_swiz_chipset = { + apecs_swiz_inb, + apecs_swiz_inw, + apecs_swiz_inl, + apecs_swiz_outb, + apecs_swiz_outw, + apecs_swiz_outl, + apecs_swiz_readb, + apecs_swiz_readw, + apecs_swiz_readl, + apecs_swiz_writeb, + apecs_swiz_writew, + apecs_swiz_writel, + apecs_swiz_maxdevs, + apecs_swiz_cfgreadb, + apecs_swiz_cfgreadw, + apecs_swiz_cfgreadl, + apecs_swiz_cfgwriteb, + apecs_swiz_cfgwritew, + apecs_swiz_cfgwritel, +}; + +static int +apecs_swiz_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + + + +static u_int8_t +apecs_swiz_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(APECS_PCI_SIO), port); +} + +static u_int16_t +apecs_swiz_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(APECS_PCI_SIO), port); +} + +static u_int32_t +apecs_swiz_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(APECS_PCI_SIO), port); +} + +static void +apecs_swiz_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * Memory functions. + * + * XXX linux does 32-bit reads/writes via dense space. This doesn't + * appear to work for devices behind a ppb. I'm using sparse + * accesses & they appear to work just fine everywhere. + */ + +static u_int32_t apecs_hae_mem; + +#define REG1 (1UL << 24) +static __inline void +apecs_swiz_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != apecs_hae_mem) { + apecs_hae_mem = msb; + REGVAL(EPIC_HAXR1) = apecs_hae_mem; + alpha_mb(); + apecs_hae_mem = REGVAL(EPIC_HAXR1); + } + splx(s); + } +} + +static u_int8_t +apecs_swiz_readb(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(APECS_PCI_SPARSE), pa); +} + +static u_int16_t +apecs_swiz_readw(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(APECS_PCI_SPARSE), pa); +} + +static u_int32_t +apecs_swiz_readl(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa); +} + +static void +apecs_swiz_writeb(u_int32_t pa, u_int8_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +apecs_swiz_writew(u_int32_t pa, u_int16_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + + +static void +apecs_swiz_writel(u_int32_t pa, u_int32_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); + +} + + +#define APECS_SWIZ_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) { \ + do { \ + (s) = splhigh(); \ + (old_haxr2) = REGVAL(EPIC_HAXR2); \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1; \ + alpha_mb(); \ + } while(0); \ +} + +#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2); \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define SWIZ_CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return val; + +#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return; + +#if 1 +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t); +} + +#else +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return ~0; + return SPARSE_READ_BYTE(sc->cfg0_base, off); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return ~0; + return SPARSE_READ_WORD(sc->cfg0_base, off); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0; + return SPARSE_READ_LONG(sc->cfg0_base, off); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return; + SPARSE_WRITE_BYTE(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return; + SPARSE_WRITE_WORD(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return; + SPARSE_WRITE_LONG(sc->cfg0_base, off, data); + alpha_wmb(); +} +#endif + +static int apecs_probe(device_t dev); +static int apecs_attach(device_t dev); +static void *apecs_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int apecs_connect_intr(device_t dev, void* ih); + +static device_method_t apecs_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, apecs_probe), + DEVMETHOD(device_attach, apecs_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t apecs_driver = { + "apecs", + apecs_methods, + DRIVER_TYPE_MISC, + sizeof(struct apecs_softc), +}; + +void +apecs_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = apecs_swiz_chipset; +} + +static int +apecs_probe(device_t dev) +{ + int memwidth; + if (apecs0) + return ENXIO; + apecs0 = dev; + memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64; + if(memwidth == 64){ + device_set_desc(dev, "DECchip 21071 Core Logic chipset"); + } else { + device_set_desc(dev, "DECchip 21072 Core Logic chipset"); + } + apecs_hae_mem = REGVAL(EPIC_HAXR1); + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +extern void isa_intr(void* frame, u_long vector); + +static int +apecs_attach(device_t dev) +{ + struct apecs_softc* sc = APECS_SOFTC(dev); + apecs_init(); + chipset.intrdev = isa0; + + sc->dmem_base = APECS_PCI_DENSE; + sc->smem_base = APECS_PCI_SPARSE; + sc->io_base = APECS_PCI_SIO; + sc->cfg0_base = KV(APECS_PCI_CONF); + sc->cfg1_base = NULL; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0); + diff --git a/sys/alpha/pci/apecsreg.h b/sys/alpha/pci/apecsreg.h new file mode 100644 index 000000000000..66e2c5e6f1ae --- /dev/null +++ b/sys/alpha/pci/apecsreg.h @@ -0,0 +1,343 @@ +/* $NetBSD: apecsreg.h,v 1.7 1997/06/06 23:54:24 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * APECS Chipset registers and constants. + * + * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data + * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38. + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */ +#define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */ +#define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */ +#define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */ + + +/* + * 21071-CA Registers + */ + +/* + * 21071-CA General Registers + */ +#define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */ +#define COMANCHE_GCR_RSVD 0xc009 +#define COMANCHE_GCR_SYSARB 0x0006 +#define COMANCHE_GCR_WIDEMEM 0x0010 +#define COMANCHE_GCR_BC_EN 0x0020 +#define COMANCHE_GCR_BC_NOALLOC 0x0040 +#define COMANCHE_GCR_BC_LONGWR 0x0080 +#define COMANCHE_GCR_BC_IGNTAG 0x0100 +#define COMANCHE_GCR_BC_FRCTAG 0x0200 +#define COMANCHE_GCR_BC_FRCD 0x0400 +#define COMANCHE_GCR_BC_FRCV 0x0800 +#define COMANCHE_GCR_BC_FRCP 0x1000 +#define COMANCHE_GCR_BC_BADAP 0x2000 + +#define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */ + +#define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */ +#define COMANCHE_ED_LOSTERR 0x0001 +#define COMANCHE_ED_BC_TAPERR 0x0002 +#define COMANCHE_ED_BC_TCPERR 0x0004 +#define COMANCHE_ED_NXMERR 0x0008 +#define COMANCHE_ED_DMACAUSE 0x0010 +#define COMANCHE_ED_VICCAUSE 0x0020 +#define COMANCHE_ED_CREQCAUSE 0x01c0 +#define COMANCHE_ED_RSVD 0x1e00 +#define COMANCHE_ED_PASS2 0x2000 +#define COMANCHE_ED_IDXLLOCK 0x4000 +#define COMANCHE_ED_WRPEND 0x8000 + +#define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */ +#define COMANCHE_TAGENB_RSVD 0x0001 + +#define COMANCHE_TAGENB_C_4G 0x0000 +#define COMANCHE_TAGENB_C_2G 0x8000 +#define COMANCHE_TAGENB_C_1G 0xc000 +#define COMANCHE_TAGENB_C_512M 0xe000 +#define COMANCHE_TAGENB_C_256M 0xf000 +#define COMANCHE_TAGENB_C_128M 0xf800 +#define COMANCHE_TAGENB_C_64M 0xfc00 +#define COMANCHE_TAGENB_C_32M 0xfe00 +#define COMANCHE_TAGENB_C_16M 0xff00 +#define COMANCHE_TAGENB_C_8M 0xff80 +#define COMANCHE_TAGENB_C_4M 0xffc0 +#define COMANCHE_TAGENB_C_2M 0xffe0 +#define COMANCHE_TAGENB_C_1M 0xfff0 +#define COMANCHE_TAGENB_C_512K 0xfff8 +#define COMANCHE_TAGENB_C_256K 0xfffc +#define COMANCHE_TAGENB_C_128K 0xfffe + +#define COMANCHE_TAGENB_M_4G 0xffff +#define COMANCHE_TAGENB_M_2G 0x7fff +#define COMANCHE_TAGENB_M_1G 0x3fff +#define COMANCHE_TAGENB_M_512M 0x1fff +#define COMANCHE_TAGENB_M_256M 0x0fff +#define COMANCHE_TAGENB_M_128M 0x07ff +#define COMANCHE_TAGENB_M_64M 0x03ff +#define COMANCHE_TAGENB_M_32M 0x01ff +#define COMANCHE_TAGENB_M_16M 0x00ff +#define COMANCHE_TAGENB_M_8M 0x007f +#define COMANCHE_TAGENB_M_4M 0x003f +#define COMANCHE_TAGENB_M_2M 0x001f +#define COMANCHE_TAGENB_M_1M 0x000e +#define COMANCHE_TAGENB_M_512K 0x0006 +#define COMANCHE_TAGENB_M_256K 0x0002 +#define COMANCHE_TAGENB_M_128K 0x0000 + +#define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */ + +#define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */ +#define COMANCHE_ERR_HI_RSVD 0xe000 + +#define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */ + +#define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +/* + * 21071-CA Memory Registers + */ +#define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +#define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */ + +#define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */ +#define COMANCHE_VFP_COL 0x001f +#define COMANCHE_VFP_ROW 0x3fe0 +#define COMANCHE_VFP_SUBBANK 0x4000 +#define COMANCHE_VFP_RSVD 0x8000 + +#define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */ + +#define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */ + +/* + * 21071-CA Memory banks' Base Address Register format + */ +#define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */ +#define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */ +#define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */ +#define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */ +#define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */ +#define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */ +#define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */ +#define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */ +#define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */ +#define COMANCHE_BAR_RSVD 0x001f + +/* + * 21071-CA Memory banks' Configuration Register format + */ +#define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */ +#define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */ +#define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */ +#define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */ +#define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */ +#define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */ +#define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */ +#define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */ +#define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */ +#define COMANCHE_CR_VALID 0x0001 +#define COMANCHE_CR_SIZE 0x001e +#define COMANCHE_CR_SUBENA 0x0020 +#define COMANCHE_CR_COLSEL 0x01c0 +#define COMANCHE_CR_S0_RSVD 0xfe00 +#define COMANCHE_CR_S8_CHECK 0x0200 +#define COMANCHE_CR_S8_RSVD 0xfc00 + +/* + * 21071-CA Memory banks' Timing Register A format + */ +#define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */ +#define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */ +#define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */ +#define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */ +#define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */ +#define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */ +#define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */ +#define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */ +#define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */ +#define COMANCHE_TRA_ROWSETUP 0x0003 +#define COMANCHE_TRA_ROWHOLD 0x000c +#define COMANCHE_TRA_COLSETUP 0x0070 +#define COMANCHE_TRA_COLHOLD 0x0180 +#define COMANCHE_TRA_RDLYROW 0x0e00 +#define COMANCHE_TRA_RDLYCOL 0x7000 +#define COMANCHE_TRA_RSVD 0x8000 + +/* + * 21071-CA Memory banks' Timing Register B format + */ +#define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */ +#define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */ +#define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */ +#define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */ +#define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */ +#define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */ +#define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */ +#define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */ +#define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */ +#define COMANCHE_TRB_RTCAS 0x0007 +#define COMANCHE_TRB_WTCAS 0x0038 +#define COMANCHE_TRB_TCP 0x00c0 +#define COMANCHE_TRB_WHOLD0ROW 0x0700 +#define COMANCHE_TRB_WHOLD0COL 0x3800 +#define COMANCHE_TRB_RSVD 0xc000 + + +/* + * 21071-DA Registers + */ +#define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */ +#define EPIC_DCSR_TENB 0x00000001 +#define EPIC_DCSR_RSVD 0x7fc00082 +#define EPIC_DCSR_PENB 0x00000004 +#define EPIC_DCSR_DCEI 0x00000008 +#define EPIC_DCSR_DPEC 0x00000010 +#define EPIC_DCSR_IORT 0x00000020 +#define EPIC_DCSR_LOST 0x00000040 +#define EPIC_DCSR_DDPE 0x00000100 +#define EPIC_DCSR_IOPE 0x00000200 +#define EPIC_DCSR_TABT 0x00000400 +#define EPIC_DCSR_NDEV 0x00000800 +#define EPIC_DCSR_CMRD 0x00001000 +#define EPIC_DCSR_UMRD 0x00002000 +#define EPIC_DCSR_IPTL 0x00004000 +#define EPIC_DCSR_MERR 0x00008000 +#define EPIC_DCSR_DBYP 0x00030000 +#define EPIC_DCSR_PCMD 0x003c0000 +#define EPIC_DCSR_PASS2 0x80000000 + +#define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */ + +#define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */ +#define EPIC_SEAR_RSVD 0x0000000f +#define EPIC_SEAR_SYS_ERR 0xfffffff0 + +#define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */ +#define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */ +#define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */ + +#define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */ +#define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */ +#define EPIC_TBASE_RSVD 0x000001ff +#define EPIC_TBASE_T_BASE 0xfffffe00 +#define EPIC_TBASE_SHIFT 1 + +#define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */ +#define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */ +#define EPIC_PCI_BASE_RSVD 0x0003ffff +#define EPIC_PCI_BASE_SGEN 0x00040000 +#define EPIC_PCI_BASE_WENB 0x00080000 +#define EPIC_PCI_BASE_PCI_BASE 0xfff00000 + +#define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */ +#define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */ +#define EPIC_PCI_MASK_RSVD 0x000fffff +#define EPIC_PCI_MASK_PCI_MASK 0xfff00000 +#define EPIC_PCI_MASK_1M 0x00000000 +#define EPIC_PCI_MASK_2M 0x00100000 +#define EPIC_PCI_MASK_4M 0x00300000 +#define EPIC_PCI_MASK_8M 0x00700000 +#define EPIC_PCI_MASK_16M 0x00f00000 +#define EPIC_PCI_MASK_32M 0x01f00000 +#define EPIC_PCI_MASK_64M 0x03f00000 +#define EPIC_PCI_MASK_128M 0x07f00000 +#define EPIC_PCI_MASK_256M 0x0ff00000 +#define EPIC_PCI_MASK_512M 0x1ff00000 +#define EPIC_PCI_MASK_1G 0x3ff00000 +#define EPIC_PCI_MASK_2G 0x7ff00000 +#define EPIC_PCI_MASK_4G 0xfff00000 + +#define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */ + +#define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */ +#define EPIC_HAXR1_RSVD 0x07ffffff +#define EPIC_HAXR1_EADDR 0xf8000000 + +#define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */ +#define EPIC_HAXR2_CONF_TYPE 0x00000003 +#define EPIC_HAXR2_CONF_TYPO0 0x00000000 +#define EPIC_HAXR2_CONF_TYPE1 0x00000001 +#define EPIC_HAXR2_RSVD 0x00fffffc +#define EPIC_HAXR2_EADDR 0xff000000 + +#define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */ +#define EPIC_PMLT_PMLC 0x000000ff +#define EPIC_PMLT_RSVD 0xffffff00 + +#define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */ +#define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */ +#define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */ +#define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */ +#define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */ +#define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */ +#define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */ +#define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */ +#define EPIC_TLB_TAG_RSVD 0x00000fff +#define EPIC_TLB_TAG_EVAL 0x00001000 +#define EPIC_TLB_TAG_PCI_PAGE 0xffffe000 + +#define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */ +#define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */ +#define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */ +#define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */ +#define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */ +#define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */ +#define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */ +#define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */ +#define EPIC_TLB_DATA_RSVD 0xffe00001 +#define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe + +#define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */ + +/* + * EPIC Scatter-Gather Map Entries + */ + +struct sgmapent { + u_int64_t val; +}; +#define SGMAPENT_EVAL 0x0000000000000001L +#define SGMAPENT_PFN 0x00000000001ffffeL +#define SGMAPENT_RSVD 0xffffffffffe00000L + +#define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1)) diff --git a/sys/alpha/pci/apecsvar.h b/sys/alpha/pci/apecsvar.h new file mode 100644 index 000000000000..0104b4fbb246 --- /dev/null +++ b/sys/alpha/pci/apecsvar.h @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: ciavar.h,v 1.1 1998/07/05 12:16:15 dfr Exp $ + */ + +extern void apecs_init(void); + diff --git a/sys/alpha/pci/cia.c b/sys/alpha/pci/cia.c index 25f87016af72..9b33ac894e22 100644 --- a/sys/alpha/pci/cia.c +++ b/sys/alpha/pci/cia.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: cia.c,v 1.4 1998/07/31 09:17:51 dfr Exp $ + * $Id: cia.c,v 1.5 1998/08/07 08:18:44 dfr Exp $ */ #include <sys/param.h> @@ -45,16 +45,8 @@ static devclass_t cia_devclass; static device_t cia0; /* XXX only one for now */ static u_int32_t cia_hae_mem; -extern void eb164_intr_enable(int irq); -extern void eb164_intr_disable(int irq); -static void cia_intr(void* frame, u_long vector); - struct cia_softc { - vm_offset_t dmem_base; /* dense memory */ - vm_offset_t smem_base; /* sparse memory */ - vm_offset_t io_base; /* dense i/o */ - vm_offset_t cfg0_base; /* dense pci0 config */ - vm_offset_t cfg1_base; /* dense pci1 config */ + int junk; /* no softc */ }; #define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev) @@ -415,9 +407,8 @@ cia_swiz_maxdevs(u_int b) type val = ~0; \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ @@ -429,9 +420,8 @@ cia_swiz_maxdevs(u_int b) #define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ @@ -515,6 +505,13 @@ cia_init() else chipset = cia_bwx_chipset; cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM); + +#if 0 + chipset = cia_swiz_chipset; /* XXX */ +#endif + + if (platform.pci_intr_init) + platform.pci_intr_init(); } static int @@ -536,22 +533,10 @@ cia_attach(device_t dev) struct cia_softc* sc = CIA_SOFTC(dev); cia_init(); - chipset.bridge = dev; - - if (alpha_amask(ALPHA_AMASK_BWX) == 0) { - sc->dmem_base = CIA_EV56_BWMEM; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_EV56_BWIO; - sc->cfg0_base = CIA_EV56_BWCONF0; - sc->cfg1_base = CIA_EV56_BWCONF1; - } else { - sc->dmem_base = CIA_PCI_DENSE; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_PCI_SIO1; - sc->cfg0_base = KV(CIA_PCI_CONF); - sc->cfg1_base = NULL; - } - set_iointr(cia_intr); + chipset.intrdev = dev; + + if (!platform.iointr) /* XXX */ + set_iointr(alpha_dispatch_intr); bus_generic_attach(dev); return 0; @@ -561,7 +546,7 @@ static void * cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg) { - return alpha_create_intr(irq, intr, arg); + return alpha_create_intr(0x900 + (irq << 4), intr, arg); } static int @@ -571,22 +556,12 @@ cia_connect_intr(device_t dev, void* ih) int s = splhigh(); int error = alpha_connect_intr(i); if (!error) { - if (i->vector > 0x900) - /* PCI interrupt */ - platform.pci_intr_enable((i->vector - 0x900) >> 4); - else if (i->vector > 0x800) - /* ISA interrupt chained to PCI interrupt 4 */ - platform.pci_intr_enable(4);/* XXX */ + /* Enable PCI interrupt */ + platform.pci_intr_enable((i->vector - 0x900) >> 4); } splx(s); return error; } -static void -cia_intr(void* frame, u_long vector) -{ - alpha_dispatch_intr(vector); -} - DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0); diff --git a/sys/alpha/pci/lca.c b/sys/alpha/pci/lca.c new file mode 100644 index 000000000000..739d3f0ee901 --- /dev/null +++ b/sys/alpha/pci/lca.c @@ -0,0 +1,371 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/bus.h> + +#include <alpha/pci/lcareg.h> +#include <alpha/pci/lcavar.h> +#include <machine/swiz.h> +#include <machine/intr.h> +#include <machine/cpuconf.h> + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t lca_devclass; +static device_t lca0; /* XXX only one for now */ +static device_t isa0; + +struct lca_softc { + int junk; +}; + +#define LCA_SOFTC(dev) (struct lca_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t lca_inb; +static alpha_chipset_inw_t lca_inw; +static alpha_chipset_inl_t lca_inl; +static alpha_chipset_outb_t lca_outb; +static alpha_chipset_outw_t lca_outw; +static alpha_chipset_outl_t lca_outl; +static alpha_chipset_readb_t lca_readb; +static alpha_chipset_readw_t lca_readw; +static alpha_chipset_readl_t lca_readl; +static alpha_chipset_writeb_t lca_writeb; +static alpha_chipset_writew_t lca_writew; +static alpha_chipset_writel_t lca_writel; +static alpha_chipset_maxdevs_t lca_maxdevs; +static alpha_chipset_cfgreadb_t lca_cfgreadb; +static alpha_chipset_cfgreadw_t lca_cfgreadw; +static alpha_chipset_cfgreadl_t lca_cfgreadl; +static alpha_chipset_cfgwriteb_t lca_cfgwriteb; +static alpha_chipset_cfgwritew_t lca_cfgwritew; +static alpha_chipset_cfgwritel_t lca_cfgwritel; + +static alpha_chipset_t lca_chipset = { + lca_inb, + lca_inw, + lca_inl, + lca_outb, + lca_outw, + lca_outl, + lca_readb, + lca_readw, + lca_readl, + lca_writeb, + lca_writew, + lca_writel, + lca_maxdevs, + lca_cfgreadb, + lca_cfgreadw, + lca_cfgreadl, + lca_cfgwriteb, + lca_cfgwritew, + lca_cfgwritel, +}; + +static u_int8_t +lca_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(LCA_PCI_SIO), port); +} + +static u_int16_t +lca_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(LCA_PCI_SIO), port); +} + +static u_int32_t +lca_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(LCA_PCI_SIO), port); +} + +static void +lca_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * The LCA HAE is write-only. According to NetBSD, this is where it starts. + */ +static u_int32_t lca_hae_mem = 0x80000000; + +/* + * The first 16Mb ignores the HAE. The next 112Mb uses the HAE to set + * the high bits of the PCI address. + */ +#define REG1 (1UL << 24) + +static __inline void +lca_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != lca_hae_mem) { + lca_hae_mem = msb; + REGVAL(LCA_IOC_HAE) = lca_hae_mem; + alpha_mb(); + alpha_mb(); + } + splx(s); + } +} + +static u_int8_t +lca_readb(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(LCA_PCI_SPARSE), pa); +} + +static u_int16_t +lca_readw(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(LCA_PCI_SPARSE), pa); +} + +static u_int32_t +lca_readl(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(LCA_PCI_SPARSE), pa); +} + +static void +lca_writeb(u_int32_t pa, u_int8_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writew(u_int32_t pa, u_int16_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writel(u_int32_t pa, u_int32_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static int +lca_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + +#define LCA_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define LCA_TYPE1_SETUP(b,s) if ((b)) { \ + do { \ + (s) = splhigh(); \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 1; \ + alpha_mb(); \ + } while(0); \ +} + +#define LCA_TYPE1_TEARDOWN(b,s) if ((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 0; \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return val + +#define CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return + +static u_int8_t +lca_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +lca_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +lca_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +lca_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +lca_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +lca_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + CFGWRITE(b, s, f, r, data, LONG, u_int16_t); +} + +static int lca_probe(device_t dev); +static int lca_attach(device_t dev); +static void *lca_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int lca_connect_intr(device_t dev, void* ih); + +static device_method_t lca_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lca_probe), + DEVMETHOD(device_attach, lca_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t lca_driver = { + "lca", + lca_methods, + DRIVER_TYPE_MISC, + sizeof(struct lca_softc), +}; + +void +lca_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + /* Type 0 PCI conf access. */ + REGVAL64(LCA_IOC_CONF) = 0; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = lca_chipset; +} + +static int +lca_probe(device_t dev) +{ + if (lca0) + return ENXIO; + lca0 = dev; + device_set_desc(dev, "21066 PCI adapter"); /* XXX */ + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +static int +lca_attach(device_t dev) +{ + struct lca_softc* sc = LCA_SOFTC(dev); + + lca_init(); + chipset.intrdev = isa0; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(lca, root, lca_driver, lca_devclass, 0, 0); + diff --git a/sys/alpha/pci/lcareg.h b/sys/alpha/pci/lcareg.h new file mode 100644 index 000000000000..f7a655ca387f --- /dev/null +++ b/sys/alpha/pci/lcareg.h @@ -0,0 +1,95 @@ +/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Authors: Jeffrey Hsu, Jason R. Thorpe + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * 21066 chip registers + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) +#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */ +#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */ + +#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */ +#define IOC_HAE_ADDREXT 0x00000000f8000000UL +#define IOC_HAE_RSVSD 0xffffffff07ffffffUL + +#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */ + +#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */ +#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */ +#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */ +#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */ +#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */ +#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */ +#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */ +#define IOC_STAT0_CODESHIFT 8 +#define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */ + +#define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */ +#define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */ + +#define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */ +#define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */ +#define IOC_TB_ENA_TEN 0x0000000000000080UL + +#define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100) /* Window Base */ +#define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140) /* Window Mask */ +#define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */ + +#define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */ +#define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160) /* Window Mask */ +#define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */ + +#define IOC_W_BASE_W_BASE 0x00000000fff00000UL /* Window base value */ +#define IOC_W_BASE_SG 0x0000000100000000UL /* Window uses SGMAPs */ +#define IOC_W_BASE_WEN 0x0000000200000000UL /* Window enable */ + +#define IOC_W_MASK_1M 0x0000000000000000UL /* 1MB window */ +#define IOC_W_MASK_2M 0x0000000000100000UL /* 2MB window */ +#define IOC_W_MASK_4M 0x0000000000300000UL /* 4MB window */ +#define IOC_W_MASK_8M 0x0000000000700000UL /* 8MB window */ +#define IOC_W_MASK_16M 0x0000000000f00000UL /* 16MB window */ +#define IOC_W_MASK_32M 0x0000000001f00000UL /* 32MB window */ +#define IOC_W_MASK_64M 0x0000000003f00000UL /* 64MB window */ +#define IOC_W_MASK_128M 0x0000000007f00000UL /* 128M window */ +#define IOC_W_MASK_256M 0x000000000ff00000UL /* 256M window */ +#define IOC_W_MASK_512M 0x000000001ff00000UL /* 512M window */ +#define IOC_W_MASK_1G 0x000000003ff00000UL /* 1GB window */ +#define IOC_W_MASK_2G 0x000000007ff00000UL /* 2GB window */ +#define IOC_W_MASK_4G 0x00000000fff00000UL /* 4GB window */ + +#define IOC_W_T_BASE 0x00000000fffffc00UL /* page table base */ diff --git a/sys/alpha/pci/lcavar.h b/sys/alpha/pci/lcavar.h new file mode 100644 index 000000000000..53f036dea007 --- /dev/null +++ b/sys/alpha/pci/lcavar.h @@ -0,0 +1,29 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +extern void lca_init(void); diff --git a/sys/alpha/pci/pcibus.c b/sys/alpha/pci/pcibus.c index 2735fd1cd932..a350772e8853 100644 --- a/sys/alpha/pci/pcibus.c +++ b/sys/alpha/pci/pcibus.c @@ -23,7 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcibus.c,v 1.2 1998/07/12 16:16:20 dfr Exp $ + * $Id: pcibus.c,v 1.3 1998/07/22 08:33:30 dfr Exp $ * */ @@ -98,10 +98,9 @@ struct intrec * intr_create(void *dev_instance, int irq, inthand2_t handler, void *arg, intrmask_t *maskptr, int flags) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) - return BUS_CREATE_INTR(pcib, pcib, - 0x900 + (irq << 4), + return BUS_CREATE_INTR(pcib, pcib, irq, (driver_intr_t*) handler, arg); else return 0; @@ -110,7 +109,7 @@ intr_create(void *dev_instance, int irq, inthand2_t handler, void *arg, int intr_connect(struct intrec *idesc) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) return BUS_CONNECT_INTR(pcib, idesc); else diff --git a/sys/alpha/tlsb/dwlpx.c b/sys/alpha/tlsb/dwlpx.c index 0864b7bedca8..2f300ebc8cd0 100644 --- a/sys/alpha/tlsb/dwlpx.c +++ b/sys/alpha/tlsb/dwlpx.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: dwlpx.c,v 1.3 1998/07/12 16:23:13 dfr Exp $ + * $Id: dwlpx.c,v 1.4 1998/07/16 13:38:35 dfr Exp $ */ #include "opt_simos.h" @@ -272,7 +272,7 @@ dwlpx_attach(device_t dev) dwlpx0 = dev; chipset = dwlpx_chipset; - chipset.bridge = dev; + chipset.intrdev = dev; regs = KV(DWLPX_BASE(kft_get_node(dev), kft_get_hosenum(dev))); sc->dmem_base = regs + (0L << 32); diff --git a/sys/conf/Makefile.alpha b/sys/conf/Makefile.alpha index c98b3d7e2a38..290b24ce4df5 100644 --- a/sys/conf/Makefile.alpha +++ b/sys/conf/Makefile.alpha @@ -1,7 +1,7 @@ # Makefile.alpha -- with config changes. # Copyright 1990 W. Jolitz # from: @(#)Makefile.alpha 7.1 5/10/91 -# $Id: Makefile.alpha,v 1.5 1998/07/22 08:23:26 dfr Exp $ +# $Id: Makefile.alpha,v 1.6 1998/07/30 08:12:14 dfr Exp $ # # Makefile for FreeBSD # @@ -79,7 +79,7 @@ SYSTEM_LD_HEAD= @echo loading $@; rm -f $@ .if ${BINFORMAT} == elf SYSTEM_OBJS= locore.o setdef0.o vnode_if.o \ ${OBJS} ioconf.o param.o config.o \ - setdef1.o + setdef1.o hack.so SYSTEM_LD= @${LD} --export-dynamic -T$S/alpha/conf/kernel.script -e locorestart \ -o $@ -X ${SYSTEM_OBJS} vers.o SYSTEM_LD_TAIL= @${SIZE} $@; chmod 755 $@ @@ -119,6 +119,11 @@ symbols.sort: ${ALPHA}/alpha/symbols.raw locore.o: ${ALPHA}/alpha/locore.s assym.s ${NORMAL_S} +hack.so: Makefile + echo "void __elf_kld_hack() {}" > hack.c + ${CC} -shared -nostdlib hack.c -o hack.so + rm -f hack.c + setdef0.o: ${ALPHA}/alpha/setdef0.c setdefs.h ${NORMAL_C} diff --git a/sys/conf/files.alpha b/sys/conf/files.alpha index 396d707fb354..5e28c2c43f2d 100644 --- a/sys/conf/files.alpha +++ b/sys/conf/files.alpha @@ -1,7 +1,7 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # -# $Id: files.alpha,v 1.3 1998/07/12 16:26:52 dfr Exp $ +# $Id: files.alpha,v 1.4 1998/07/22 08:24:39 dfr Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and @@ -19,6 +19,9 @@ alpha/alpha/cpuconf.c standard alpha/alpha/dec_kn8ae.c optional dec_kn8ae alpha/alpha/dec_eb164.c optional dec_eb164 alpha/alpha/dec_kn20aa.c optional dec_kn20aa +alpha/alpha/dec_2100_a50.c optional dec_2100_a50 +alpha/alpha/dec_st550.c optional dec_st550 +alpha/alpha/dec_axppci_33.c optional dec_axppci_33 alpha/alpha/mountroot.c optional slice alpha/alpha/ipl_funcs.c standard alpha/alpha/pal.s standard @@ -79,6 +82,8 @@ mcclock_if.h standard \ alpha/pci/cia.c optional cia alpha/pci/pci_eb164_intr.s optional cia alpha/isa/mcclock_isa.c optional cia +alpha/pci/apecs.c optional apecs +alpha/pci/lca.c optional lca alpha/pci/pcibus.c optional pci alpha/isa/isa.c optional isa kern/link_elf.c standard diff --git a/sys/conf/ldscript.alpha b/sys/conf/ldscript.alpha index eac78dd31df4..1bcfd9079bb2 100644 --- a/sys/conf/ldscript.alpha +++ b/sys/conf/ldscript.alpha @@ -3,8 +3,7 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/sys/conf/ldscript.powerpc b/sys/conf/ldscript.powerpc index eac78dd31df4..1bcfd9079bb2 100644 --- a/sys/conf/ldscript.powerpc +++ b/sys/conf/ldscript.powerpc @@ -3,8 +3,7 @@ OUTPUT_FORMAT("elf64-alpha", "elf64-alpha", OUTPUT_ARCH(alpha) ENTRY(__start) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/egcs/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/egcs/alphaev5-unknown-linux-gnu/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + kernel_text = 0xfffffc0000300000; SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/sys/conf/options.alpha b/sys/conf/options.alpha index f626ca22e569..3132f9ad5bbe 100644 --- a/sys/conf/options.alpha +++ b/sys/conf/options.alpha @@ -1,9 +1,12 @@ -# $Id: options.alpha,v 1.2 1998/07/12 16:28:09 dfr Exp $ +# $Id: options.alpha,v 1.3 1998/07/22 08:24:39 dfr Exp $ EV5 opt_global.h DEC_KN8AE opt_cpu.h DEC_EB164 opt_cpu.h DEC_KN20AA opt_cpu.h +DEC_2100_A50 opt_cpu.h +DEC_ST550 opt_cpu.h +DEC_AXPPCI_33 opt_cpu.h ATAPI opt_atapi.h ATAPI_STATIC opt_atapi.h |