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author | Ed Schouten <ed@FreeBSD.org> | 2009-06-22 08:08:12 +0000 |
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committer | Ed Schouten <ed@FreeBSD.org> | 2009-06-22 08:08:12 +0000 |
commit | b2f21fb044b6b5c52cff6227f9f79ca4ed42b18f (patch) | |
tree | 86c1bc482baa6c81fc70b8d715153bfa93377186 /test/CodeGen/X86 | |
parent | 600c6fa13de5c407dc36dbb0ab73807868741ae0 (diff) | |
download | src-b2f21fb044b6b5c52cff6227f9f79ca4ed42b18f.tar.gz src-b2f21fb044b6b5c52cff6227f9f79ca4ed42b18f.zip |
Update LLVM sources to r73879.vendor/llvm/llvm-r73879
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=194612
svn path=/vendor/llvm/llvm-r73879/; revision=194614; tag=vendor/llvm/llvm-r73879
Diffstat (limited to 'test/CodeGen/X86')
-rw-r--r-- | test/CodeGen/X86/2009-06-15-not-a-tail-call.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/X86/fmul-zero.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/inline-asm-fpstack2.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/X86/iv-users-in-other-loops.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/X86/optimize-max-0.ll (renamed from test/CodeGen/X86/optimize-smax.ll) | 229 | ||||
-rw-r--r-- | test/CodeGen/X86/optimize-max-1.ll | 78 | ||||
-rw-r--r-- | test/CodeGen/X86/optimize-max-2.ll | 30 | ||||
-rw-r--r-- | test/CodeGen/X86/pic_jumptable.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tls1-pic.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tls1.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tls2-pic.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/tls3-pic.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tls4-pic.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/umul-with-overflow.ll | 8 |
15 files changed, 390 insertions, 14 deletions
diff --git a/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll b/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll new file mode 100644 index 000000000000..095e6a103621 --- /dev/null +++ b/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | not grep TAILCALL + +; Bug 4396. This tail call can NOT be optimized. + +declare fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() nounwind + +define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind { +entry: + %tmp6 = tail call fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() ; <i8*> [#uses=2] + %tmp9 = tail call i8* @memset(i8* %tmp6, i32 0, i64 2) ; <i8*> [#uses=0] + ret i8* %tmp6 +} + +declare i8* @memset(i8*, i32, i64) diff --git a/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll new file mode 100644 index 000000000000..d6ff5b6803e3 --- /dev/null +++ b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 +; PR2484 + +define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind { +entry: +%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4,i32 +5,i32 2,i32 3> +ret <4 x float> %shuffle +} diff --git a/test/CodeGen/X86/fmul-zero.ll b/test/CodeGen/X86/fmul-zero.ll index 8f705a4d242f..73aa713de52e 100644 --- a/test/CodeGen/X86/fmul-zero.ll +++ b/test/CodeGen/X86/fmul-zero.ll @@ -3,7 +3,7 @@ define void @test14(<4 x float>*) nounwind { load <4 x float>* %0, align 1 - mul <4 x float> %2, zeroinitializer + fmul <4 x float> %2, zeroinitializer store <4 x float> %3, <4 x float>* %0, align 1 ret void } diff --git a/test/CodeGen/X86/inline-asm-fpstack2.ll b/test/CodeGen/X86/inline-asm-fpstack2.ll new file mode 100644 index 000000000000..968561826b5c --- /dev/null +++ b/test/CodeGen/X86/inline-asm-fpstack2.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86 > %t +; RUN: grep {fld %%st(0)} %t +; PR4185 + +define void @test() { +return: + call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) + call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) + ret void +} diff --git a/test/CodeGen/X86/iv-users-in-other-loops.ll b/test/CodeGen/X86/iv-users-in-other-loops.ll index 2208b2d2e0e3..a48f0616291f 100644 --- a/test/CodeGen/X86/iv-users-in-other-loops.ll +++ b/test/CodeGen/X86/iv-users-in-other-loops.ll @@ -1,11 +1,11 @@ ; RUN: llvm-as < %s | llc -march=x86-64 -f -o %t ; RUN: grep inc %t | count 1 ; RUN: grep dec %t | count 2 -; RUN: grep addq %t | count 8 -; RUN: grep addb %t | count 2 -; RUN: grep leaq %t | count 12 -; RUN: grep leal %t | count 2 -; RUN: grep movq %t | count 4 +; RUN: grep addq %t | count 13 +; RUN: not grep addb %t +; RUN: grep leaq %t | count 8 +; RUN: grep leal %t | count 4 +; RUN: grep movq %t | count 5 ; IV users in each of the loops from other loops shouldn't cause LSR ; to insert new induction variables. Previously it would create a diff --git a/test/CodeGen/X86/optimize-smax.ll b/test/CodeGen/X86/optimize-max-0.ll index 0c3be31e293f..90c14565e9a6 100644 --- a/test/CodeGen/X86/optimize-smax.ll +++ b/test/CodeGen/X86/optimize-max-0.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | llc -march=x86 | not grep cmov -; LSR should be able to eliminate the smax computations by -; making the loops use slt comparisons instead of ne comparisons. +; LSR should be able to eliminate the max computations by +; making the loops use slt/ult comparisons instead of ne comparisons. target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin9" @@ -231,6 +231,231 @@ return: ; preds = %bb20 ret void } +define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind { +entry: + %0 = mul i32 %x, %w ; <i32> [#uses=2] + %1 = mul i32 %x, %w ; <i32> [#uses=1] + %2 = udiv i32 %1, 4 ; <i32> [#uses=1] + %.sum2 = add i32 %2, %0 ; <i32> [#uses=2] + %cond = icmp eq i32 %d, 1 ; <i1> [#uses=1] + br i1 %cond, label %bb29, label %bb10.preheader + +bb10.preheader: ; preds = %entry + %3 = icmp ne i32 %x, 0 ; <i1> [#uses=1] + br i1 %3, label %bb.nph9, label %bb18.loopexit + +bb.nph7: ; preds = %bb7.preheader + %4 = mul i32 %y.08, %w ; <i32> [#uses=1] + %5 = mul i32 %y.08, %s ; <i32> [#uses=1] + %6 = add i32 %5, 1 ; <i32> [#uses=1] + %tmp8 = icmp ugt i32 1, %w ; <i1> [#uses=1] + %smax9 = select i1 %tmp8, i32 1, i32 %w ; <i32> [#uses=1] + br label %bb6 + +bb6: ; preds = %bb7, %bb.nph7 + %x.06 = phi i32 [ 0, %bb.nph7 ], [ %indvar.next7, %bb7 ] ; <i32> [#uses=3] + %7 = add i32 %x.06, %4 ; <i32> [#uses=1] + %8 = shl i32 %x.06, 1 ; <i32> [#uses=1] + %9 = add i32 %6, %8 ; <i32> [#uses=1] + %10 = getelementptr i8* %r, i32 %9 ; <i8*> [#uses=1] + %11 = load i8* %10, align 1 ; <i8> [#uses=1] + %12 = getelementptr i8* %j, i32 %7 ; <i8*> [#uses=1] + store i8 %11, i8* %12, align 1 + br label %bb7 + +bb7: ; preds = %bb6 + %indvar.next7 = add i32 %x.06, 1 ; <i32> [#uses=2] + %exitcond10 = icmp ne i32 %indvar.next7, %smax9 ; <i1> [#uses=1] + br i1 %exitcond10, label %bb6, label %bb7.bb9_crit_edge + +bb7.bb9_crit_edge: ; preds = %bb7 + br label %bb9 + +bb9: ; preds = %bb7.preheader, %bb7.bb9_crit_edge + br label %bb10 + +bb10: ; preds = %bb9 + %indvar.next11 = add i32 %y.08, 1 ; <i32> [#uses=2] + %exitcond12 = icmp ne i32 %indvar.next11, %x ; <i1> [#uses=1] + br i1 %exitcond12, label %bb7.preheader, label %bb10.bb18.loopexit_crit_edge + +bb10.bb18.loopexit_crit_edge: ; preds = %bb10 + br label %bb10.bb18.loopexit_crit_edge.split + +bb10.bb18.loopexit_crit_edge.split: ; preds = %bb.nph9, %bb10.bb18.loopexit_crit_edge + br label %bb18.loopexit + +bb.nph9: ; preds = %bb10.preheader + %13 = icmp ugt i32 %w, 0 ; <i1> [#uses=1] + br i1 %13, label %bb.nph9.split, label %bb10.bb18.loopexit_crit_edge.split + +bb.nph9.split: ; preds = %bb.nph9 + br label %bb7.preheader + +bb7.preheader: ; preds = %bb.nph9.split, %bb10 + %y.08 = phi i32 [ 0, %bb.nph9.split ], [ %indvar.next11, %bb10 ] ; <i32> [#uses=3] + br i1 true, label %bb.nph7, label %bb9 + +bb.nph5: ; preds = %bb18.loopexit + %14 = udiv i32 %w, 2 ; <i32> [#uses=1] + %15 = icmp ult i32 %w, 2 ; <i1> [#uses=1] + %16 = udiv i32 %x, 2 ; <i32> [#uses=2] + br i1 %15, label %bb18.bb20_crit_edge.split, label %bb.nph5.split + +bb.nph5.split: ; preds = %bb.nph5 + %tmp2 = icmp ugt i32 1, %16 ; <i1> [#uses=1] + %smax3 = select i1 %tmp2, i32 1, i32 %16 ; <i32> [#uses=1] + br label %bb13 + +bb13: ; preds = %bb18, %bb.nph5.split + %y.14 = phi i32 [ 0, %bb.nph5.split ], [ %indvar.next1, %bb18 ] ; <i32> [#uses=4] + %17 = mul i32 %14, %y.14 ; <i32> [#uses=2] + %18 = shl i32 %y.14, 1 ; <i32> [#uses=1] + %19 = urem i32 %y.14, 2 ; <i32> [#uses=1] + %20 = add i32 %19, %18 ; <i32> [#uses=1] + %21 = mul i32 %20, %s ; <i32> [#uses=2] + br i1 true, label %bb.nph3, label %bb17 + +bb.nph3: ; preds = %bb13 + %22 = add i32 %17, %0 ; <i32> [#uses=1] + %23 = add i32 %17, %.sum2 ; <i32> [#uses=1] + %24 = udiv i32 %w, 2 ; <i32> [#uses=2] + %tmp = icmp ugt i32 1, %24 ; <i1> [#uses=1] + %smax = select i1 %tmp, i32 1, i32 %24 ; <i32> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb15, %bb.nph3 + %x.12 = phi i32 [ 0, %bb.nph3 ], [ %indvar.next, %bb15 ] ; <i32> [#uses=5] + %25 = shl i32 %x.12, 2 ; <i32> [#uses=1] + %26 = add i32 %25, %21 ; <i32> [#uses=1] + %27 = getelementptr i8* %r, i32 %26 ; <i8*> [#uses=1] + %28 = load i8* %27, align 1 ; <i8> [#uses=1] + %.sum = add i32 %22, %x.12 ; <i32> [#uses=1] + %29 = getelementptr i8* %j, i32 %.sum ; <i8*> [#uses=1] + store i8 %28, i8* %29, align 1 + %30 = shl i32 %x.12, 2 ; <i32> [#uses=1] + %31 = or i32 %30, 2 ; <i32> [#uses=1] + %32 = add i32 %31, %21 ; <i32> [#uses=1] + %33 = getelementptr i8* %r, i32 %32 ; <i8*> [#uses=1] + %34 = load i8* %33, align 1 ; <i8> [#uses=1] + %.sum6 = add i32 %23, %x.12 ; <i32> [#uses=1] + %35 = getelementptr i8* %j, i32 %.sum6 ; <i8*> [#uses=1] + store i8 %34, i8* %35, align 1 + br label %bb15 + +bb15: ; preds = %bb14 + %indvar.next = add i32 %x.12, 1 ; <i32> [#uses=2] + %exitcond = icmp ne i32 %indvar.next, %smax ; <i1> [#uses=1] + br i1 %exitcond, label %bb14, label %bb15.bb17_crit_edge + +bb15.bb17_crit_edge: ; preds = %bb15 + br label %bb17 + +bb17: ; preds = %bb15.bb17_crit_edge, %bb13 + br label %bb18 + +bb18.loopexit: ; preds = %bb10.bb18.loopexit_crit_edge.split, %bb10.preheader + %36 = icmp ult i32 %x, 2 ; <i1> [#uses=1] + br i1 %36, label %bb20, label %bb.nph5 + +bb18: ; preds = %bb17 + %indvar.next1 = add i32 %y.14, 1 ; <i32> [#uses=2] + %exitcond4 = icmp ne i32 %indvar.next1, %smax3 ; <i1> [#uses=1] + br i1 %exitcond4, label %bb13, label %bb18.bb20_crit_edge + +bb18.bb20_crit_edge: ; preds = %bb18 + br label %bb18.bb20_crit_edge.split + +bb18.bb20_crit_edge.split: ; preds = %bb18.bb20_crit_edge, %bb.nph5 + br label %bb20 + +bb20: ; preds = %bb18.bb20_crit_edge.split, %bb18.loopexit + switch i32 %d, label %return [ + i32 3, label %bb22 + i32 1, label %bb29 + ] + +bb22: ; preds = %bb20 + %37 = mul i32 %x, %w ; <i32> [#uses=1] + %38 = udiv i32 %37, 4 ; <i32> [#uses=1] + %.sum3 = add i32 %38, %.sum2 ; <i32> [#uses=2] + %39 = add i32 %x, 15 ; <i32> [#uses=1] + %40 = and i32 %39, -16 ; <i32> [#uses=1] + %41 = add i32 %w, 15 ; <i32> [#uses=1] + %42 = and i32 %41, -16 ; <i32> [#uses=1] + %43 = mul i32 %40, %s ; <i32> [#uses=1] + %44 = icmp ugt i32 %x, 0 ; <i1> [#uses=1] + br i1 %44, label %bb.nph, label %bb26 + +bb.nph: ; preds = %bb22 + br label %bb23 + +bb23: ; preds = %bb24, %bb.nph + %y.21 = phi i32 [ 0, %bb.nph ], [ %indvar.next5, %bb24 ] ; <i32> [#uses=3] + %45 = mul i32 %y.21, %42 ; <i32> [#uses=1] + %.sum1 = add i32 %45, %43 ; <i32> [#uses=1] + %46 = getelementptr i8* %r, i32 %.sum1 ; <i8*> [#uses=1] + %47 = mul i32 %y.21, %w ; <i32> [#uses=1] + %.sum5 = add i32 %47, %.sum3 ; <i32> [#uses=1] + %48 = getelementptr i8* %j, i32 %.sum5 ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %48, i8* %46, i32 %w, i32 1) + br label %bb24 + +bb24: ; preds = %bb23 + %indvar.next5 = add i32 %y.21, 1 ; <i32> [#uses=2] + %exitcond6 = icmp ne i32 %indvar.next5, %x ; <i1> [#uses=1] + br i1 %exitcond6, label %bb23, label %bb24.bb26_crit_edge + +bb24.bb26_crit_edge: ; preds = %bb24 + br label %bb26 + +bb26: ; preds = %bb24.bb26_crit_edge, %bb22 + %49 = mul i32 %x, %w ; <i32> [#uses=1] + %.sum4 = add i32 %.sum3, %49 ; <i32> [#uses=1] + %50 = getelementptr i8* %j, i32 %.sum4 ; <i8*> [#uses=1] + %51 = mul i32 %x, %w ; <i32> [#uses=1] + %52 = udiv i32 %51, 2 ; <i32> [#uses=1] + tail call void @llvm.memset.i32(i8* %50, i8 -128, i32 %52, i32 1) + ret void + +bb29: ; preds = %bb20, %entry + %53 = add i32 %w, 15 ; <i32> [#uses=1] + %54 = and i32 %53, -16 ; <i32> [#uses=1] + %55 = icmp ugt i32 %x, 0 ; <i1> [#uses=1] + br i1 %55, label %bb.nph11, label %bb33 + +bb.nph11: ; preds = %bb29 + br label %bb30 + +bb30: ; preds = %bb31, %bb.nph11 + %y.310 = phi i32 [ 0, %bb.nph11 ], [ %indvar.next13, %bb31 ] ; <i32> [#uses=3] + %56 = mul i32 %y.310, %54 ; <i32> [#uses=1] + %57 = getelementptr i8* %r, i32 %56 ; <i8*> [#uses=1] + %58 = mul i32 %y.310, %w ; <i32> [#uses=1] + %59 = getelementptr i8* %j, i32 %58 ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %59, i8* %57, i32 %w, i32 1) + br label %bb31 + +bb31: ; preds = %bb30 + %indvar.next13 = add i32 %y.310, 1 ; <i32> [#uses=2] + %exitcond14 = icmp ne i32 %indvar.next13, %x ; <i1> [#uses=1] + br i1 %exitcond14, label %bb30, label %bb31.bb33_crit_edge + +bb31.bb33_crit_edge: ; preds = %bb31 + br label %bb33 + +bb33: ; preds = %bb31.bb33_crit_edge, %bb29 + %60 = mul i32 %x, %w ; <i32> [#uses=1] + %61 = getelementptr i8* %j, i32 %60 ; <i8*> [#uses=1] + %62 = mul i32 %x, %w ; <i32> [#uses=1] + %63 = udiv i32 %62, 2 ; <i32> [#uses=1] + tail call void @llvm.memset.i32(i8* %61, i8 -128, i32 %63, i32 1) + ret void + +return: ; preds = %bb20 + ret void +} + declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind diff --git a/test/CodeGen/X86/optimize-max-1.ll b/test/CodeGen/X86/optimize-max-1.ll new file mode 100644 index 000000000000..084e1818f5dd --- /dev/null +++ b/test/CodeGen/X86/optimize-max-1.ll @@ -0,0 +1,78 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | not grep cmov + +; LSR should be able to eliminate both smax and umax expressions +; in loop trip counts. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + +define void @fs(double* nocapture %p, i64 %n) nounwind { +entry: + %tmp = icmp slt i64 %n, 1 ; <i1> [#uses=1] + %smax = select i1 %tmp, i64 1, i64 %n ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry + %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2] + %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1] + store double 0.000000e+00, double* %scevgep, align 8 + %0 = add i64 %i.0, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %0, %smax ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +define void @bs(double* nocapture %p, i64 %n) nounwind { +entry: + %tmp = icmp sge i64 %n, 1 ; <i1> [#uses=1] + %smax = select i1 %tmp, i64 %n, i64 1 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry + %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2] + %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1] + store double 0.000000e+00, double* %scevgep, align 8 + %0 = add i64 %i.0, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %0, %smax ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +define void @fu(double* nocapture %p, i64 %n) nounwind { +entry: + %tmp = icmp eq i64 %n, 0 ; <i1> [#uses=1] + %umax = select i1 %tmp, i64 1, i64 %n ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry + %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2] + %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1] + store double 0.000000e+00, double* %scevgep, align 8 + %0 = add i64 %i.0, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %0, %umax ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +define void @bu(double* nocapture %p, i64 %n) nounwind { +entry: + %tmp = icmp ne i64 %n, 0 ; <i1> [#uses=1] + %umax = select i1 %tmp, i64 %n, i64 1 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry + %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2] + %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1] + store double 0.000000e+00, double* %scevgep, align 8 + %0 = add i64 %i.0, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %0, %umax ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} diff --git a/test/CodeGen/X86/optimize-max-2.ll b/test/CodeGen/X86/optimize-max-2.ll new file mode 100644 index 000000000000..effc3fc737d9 --- /dev/null +++ b/test/CodeGen/X86/optimize-max-2.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: grep cmov %t | count 2 +; RUN: grep jne %t | count 1 + +; LSR's OptimizeMax function shouldn't try to eliminate this max, because +; it has three operands. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + +define void @foo(double* nocapture %p, i64 %x, i64 %y) nounwind { +entry: + %tmp = icmp eq i64 %y, 0 ; <i1> [#uses=1] + %umax = select i1 %tmp, i64 1, i64 %y ; <i64> [#uses=2] + %tmp8 = icmp ugt i64 %umax, %x ; <i1> [#uses=1] + %umax9 = select i1 %tmp8, i64 %umax, i64 %x ; <i64> [#uses=1] + br label %bb4 + +bb4: ; preds = %bb4, %entry + %i.07 = phi i64 [ 0, %entry ], [ %2, %bb4 ] ; <i64> [#uses=2] + %scevgep = getelementptr double* %p, i64 %i.07 ; <double*> [#uses=2] + %0 = load double* %scevgep, align 8 ; <double> [#uses=1] + %1 = fmul double %0, 2.000000e+00 ; <double> [#uses=1] + store double %1, double* %scevgep, align 8 + %2 = add i64 %i.07, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %2, %umax9 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb4 + +return: ; preds = %bb4 + ret void +} diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index 1731feb58e91..229865bb71b9 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,6 +1,8 @@ ; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text ; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea ; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2 +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep 'lJTI' +; rdar://6971437 declare void @_Z3bari(i32) diff --git a/test/CodeGen/X86/tls1-pic.ll b/test/CodeGen/X86/tls1-pic.ll index a73e75ba8068..e43bf7ce66e6 100644 --- a/test/CodeGen/X86/tls1-pic.ll +++ b/test/CodeGen/X86/tls1-pic.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t -; RUN: grep {leal i@TLSGD(,%ebx,1), %eax} %t +; RUN: grep {leal i@TLSGD(,%ebx), %eax} %t ; RUN: grep {call ___tls_get_addr@PLT} %t ; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2 ; RUN: grep {leaq i@TLSGD(%rip), %rdi} %t2 diff --git a/test/CodeGen/X86/tls1.ll b/test/CodeGen/X86/tls1.ll index 5155dfd4a118..85ff360a5508 100644 --- a/test/CodeGen/X86/tls1.ll +++ b/test/CodeGen/X86/tls1.ll @@ -5,7 +5,7 @@ @i = thread_local global i32 15 -define i32 @f() { +define i32 @f() nounwind { entry: %tmp1 = load i32* @i ret i32 %tmp1 diff --git a/test/CodeGen/X86/tls2-pic.ll b/test/CodeGen/X86/tls2-pic.ll index cdfe97ca0b04..6ab3ee0a69fd 100644 --- a/test/CodeGen/X86/tls2-pic.ll +++ b/test/CodeGen/X86/tls2-pic.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t -; RUN: grep {leal i@TLSGD(,%ebx,1), %eax} %t +; RUN: grep {leal i@TLSGD(,%ebx), %eax} %t ; RUN: grep {call ___tls_get_addr@PLT} %t ; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2 ; RUN: grep {leaq i@TLSGD(%rip), %rdi} %t2 @@ -7,7 +7,7 @@ @i = thread_local global i32 15 -define i32* @f() { +define i32* @f() nounwind { entry: ret i32* @i } diff --git a/test/CodeGen/X86/tls3-pic.ll b/test/CodeGen/X86/tls3-pic.ll index f62cca218ab0..8e6df29afbf9 100644 --- a/test/CodeGen/X86/tls3-pic.ll +++ b/test/CodeGen/X86/tls3-pic.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t -; RUN: grep {leal i@TLSGD(,%ebx,1), %eax} %t +; RUN: grep {leal i@TLSGD(,%ebx), %eax} %t ; RUN: grep {call ___tls_get_addr@PLT} %t ; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2 ; RUN: grep {leaq i@TLSGD(%rip), %rdi} %t2 diff --git a/test/CodeGen/X86/tls4-pic.ll b/test/CodeGen/X86/tls4-pic.ll index ec3d43591cd3..94de78f7aef7 100644 --- a/test/CodeGen/X86/tls4-pic.ll +++ b/test/CodeGen/X86/tls4-pic.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic > %t -; RUN: grep {leal i@TLSGD(,%ebx,1), %eax} %t +; RUN: grep {leal i@TLSGD(,%ebx), %eax} %t ; RUN: grep {call ___tls_get_addr@PLT} %t ; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic > %t2 ; RUN: grep {leaq i@TLSGD(%rip), %rdi} %t2 diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll new file mode 100644 index 000000000000..9e69154f10f9 --- /dev/null +++ b/test/CodeGen/X86/umul-with-overflow.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep "\\\\\\\<mul" + +declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) +define i1 @a(i32 %x) zeroext nounwind { + %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3) + %obil = extractvalue {i32, i1} %res, 1 + ret i1 %obil +} |