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author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
tree | 4def12e759965de927d963ac65840d663ef9d1ea /test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll | |
parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
download | src-01095a5d43bbfde13731688ddcf6048ebb8b7721.tar.gz src-01095a5d43bbfde13731688ddcf6048ebb8b7721.zip |
Vendor import of llvm release_39 branch r276489:vendor/llvm/llvm-release_39-r276489
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=303231
svn path=/vendor/llvm/llvm-release_39-r276489/; revision=303232; tag=vendor/llvm/llvm-release_39-r276489
Diffstat (limited to 'test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll index 16abb89bb0b8..7d97777a78bd 100644 --- a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll +++ b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll @@ -8,22 +8,25 @@ ; intermediate register class copies. ; FIXME: The same register is initialized to 0 for every spill. +; FIXME: The unused arguments are removed ; GCN-LABEL: {{^}}main: -; GCN: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 -; GCN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 -; GCN-NEXT: s_mov_b32 s14, -1 -; SI-NEXT: s_mov_b32 s15, 0x80f000 -; VI-NEXT: s_mov_b32 s15, 0x800000 +; GCN-DAG: s_mov_b32 s13, s12 +; GCN-DAG: s_mov_b32 s16, SCRATCH_RSRC_DWORD0 +; GCN-DAG: s_mov_b32 s17, SCRATCH_RSRC_DWORD1 +; GCN-DAG: s_mov_b32 s18, -1 +; SI-DAG: s_mov_b32 s19, 0xe8f000 +; VI-DAG: s_mov_b32 s19, 0xe80000 -; s12 is offset user SGPR -; GCN: buffer_store_dword {{v[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 4-byte Folded Spill +; s13 is offset system SGPR +; GCN: buffer_store_dword {{v[0-9]+}}, off, s[16:19], s13 offset:{{[0-9]+}} ; 16-byte Folded Spill +; GCN: buffer_load_dword v{{[0-9]+}}, off, s[16:19], s13 offset:{{[0-9]+}} ; 16-byte Folded Reload ; GCN: NumVgprs: 256 ; GCN: ScratchSize: 1024 -define void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { +define amdgpu_vs void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { bb: %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i64 0, i64 0 %tmp11 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, align 16, !tbaa !0 @@ -172,7 +175,8 @@ bb24: ; preds = %bb157, %bb %tmp152 = phi float [ 0.000000e+00, %bb ], [ %tmp417, %bb157 ] %tmp153 = phi float [ 0.000000e+00, %bb ], [ %tmp418, %bb157 ] %tmp154 = bitcast float %tmp107 to i32 - %tmp155 = icmp sgt i32 %tmp154, 125 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 + %tmp155 = icmp sgt i32 %tmp154, %tid br i1 %tmp155, label %bb156, label %bb157 bb156: ; preds = %bb24 @@ -487,7 +491,9 @@ declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 + +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } !0 = !{!1, !1, i64 0, i32 1} |