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author	Dimitry Andric <dim@FreeBSD.org>	2015-12-30 11:46:15 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2015-12-30 11:46:15 +0000
commit	dd58ef019b700900793a1eb48b52123db01b654e (patch)
tree	fcfbb4df56a744f4ddc6122c50521dd3f1c5e196 /test/CodeGen/AMDGPU/udivrem.ll
parent	2fe5752e3a7c345cdb59e869278d36af33c13fa4 (diff)
download	src-dd58ef019b700900793a1eb48b52123db01b654e.tar.gz src-dd58ef019b700900793a1eb48b52123db01b654e.zip

Vendor import of llvm trunk r256633:

https://llvm.org/svn/llvm-project/llvm/trunk@256633

Notes

Notes: svn path=/vendor/llvm/dist/; revision=292915

Diffstat (limited to 'test/CodeGen/AMDGPU/udivrem.ll')

-rw-r--r--

test/CodeGen/AMDGPU/udivrem.ll

130

1 files changed, 65 insertions, 65 deletions

diff --git a/test/CodeGen/AMDGPU/udivrem.ll b/test/CodeGen/AMDGPU/udivrem.ll
index b3837f28209a..f692b7dfdc27 100644
--- a/test/CodeGen/AMDGPU/udivrem.ll
+++ b/test/CodeGen/AMDGPU/udivrem.ll

@@ -30,19 +30,19 @@

; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]

; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]

; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]

-; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], 0, [[RCP_LO]]

+; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]

; SI: v_cndmask_b32_e64

; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]]

-; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], [[E]], [[RCP]]

-; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], [[E]], [[RCP]]

+; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]

+; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]

; SI: v_cndmask_b32_e64

; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]]

; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[Num_S_Remainder]]

+; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]]

; SI-DAG: v_cndmask_b32_e64

; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]]

-; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], 1, [[Quotient]]

+; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]

; SI-DAG: v_subrev_i32_e32 [[Quotient_S_One:v[0-9]+]],

; SI-DAG: v_cndmask_b32_e64

@@ -110,15 +110,15 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) {

; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]

; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]

; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]

-; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]]

+; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[FIRST_RCP_LO]]

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]]

-; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]

+; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]]

+; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]]

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]

; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}}

+; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[0-9]+]], vcc, [[FIRST_Num_S_Remainder]], v{{[0-9]+}}

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]

@@ -133,15 +133,15 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) {

; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]]

; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]]

; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]]

-; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]]

+; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[SECOND_RCP_LO]]

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]]

-; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]

+; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]]

+; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]]

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]

; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}}

+; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], vcc, [[SECOND_Num_S_Remainder]], v{{[0-9]+}}

; SI-DAG: v_cndmask_b32_e64

; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]

@@ -257,83 +257,83 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3

; EG-DAG: CNDE_INT

-; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]

-; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]

-; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]

-; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]]

+; SI-DAG: v_rcp_iflag_f32_e32

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_sub_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]]

-; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]

-; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[l0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}}

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]

-; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]]

-; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]],

+; SI-DAG: v_and_b32_e32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]],

-; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]],

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]]

-; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]]

-; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]]

-; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]]

+; SI-DAG: v_rcp_iflag_f32_e32

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_sub_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]]

-; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]

-; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}}

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]

-; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]]

-; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]],

+; SI-DAG: v_and_b32_e32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]],

-; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]],

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_rcp_iflag_f32_e32 [[THIRD_RCP:v[0-9]+]]

-; SI-DAG: v_mul_hi_u32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]]

-; SI-DAG: v_mul_lo_i32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]]

-; SI-DAG: v_sub_i32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], 0, [[THIRD_RCP_LO]]

+; SI-DAG: v_rcp_iflag_f32_e32

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_sub_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]]

-; SI-DAG: v_add_i32_e32 [[THIRD_RCP_A_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[THIRD_RCP_S_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]]

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]]

-; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]]

-; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder:v[0-9]+]], [[THIRD_Num_S_Remainder]], {{v[0-9]+}}

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]]

-; SI-DAG: v_add_i32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]]

-; SI-DAG: v_subrev_i32_e32 [[THIRD_Quotient_S_One:v[0-9]+]],

+; SI-DAG: v_and_b32_e32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_add_i32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]],

-; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]],

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_rcp_iflag_f32_e32 [[FOURTH_RCP:v[0-9]+]]

-; SI-DAG: v_mul_hi_u32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]]

-; SI-DAG: v_mul_lo_i32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]]

-; SI-DAG: v_sub_i32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], 0, [[FOURTH_RCP_LO]]

+; SI-DAG: v_rcp_iflag_f32_e32

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_mul_lo_i32

+; SI-DAG: v_sub_i32_e32

; SI-DAG: v_cndmask_b32_e64

-; SI-DAG: v_mul_hi_u32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]]

-; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]

-; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]

+; SI-DAG: v_mul_hi_u32

+; SI-DAG: v_add_i32_e32

+; SI-DAG: v_subrev_i32_e32

; SI-DAG: v_cndmask_b32_e64

; SI: s_endpgm

define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {