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author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
tree | 4def12e759965de927d963ac65840d663ef9d1ea /test/CodeGen/AMDGPU/si-scheduler.ll | |
parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
download | src-01095a5d43bbfde13731688ddcf6048ebb8b7721.tar.gz src-01095a5d43bbfde13731688ddcf6048ebb8b7721.zip |
Vendor import of llvm release_39 branch r276489:vendor/llvm/llvm-release_39-r276489
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=303231
svn path=/vendor/llvm/llvm-release_39-r276489/; revision=303232; tag=vendor/llvm/llvm-release_39-r276489
Diffstat (limited to 'test/CodeGen/AMDGPU/si-scheduler.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/si-scheduler.ll | 61 |
1 files changed, 33 insertions, 28 deletions
diff --git a/test/CodeGen/AMDGPU/si-scheduler.ll b/test/CodeGen/AMDGPU/si-scheduler.ll index 66a9571d75bf..5520fe61d867 100644 --- a/test/CodeGen/AMDGPU/si-scheduler.ll +++ b/test/CodeGen/AMDGPU/si-scheduler.ll @@ -1,4 +1,9 @@ -; RUN: llc -march=amdgcn -mcpu=SI --misched=si < %s | FileCheck %s +; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so +; we need to disable this when the si scheduler is being used. +; The only way the subtarget knows that the si machine scheduler is being used +; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend +; won't know what scheduler we are using. +; RUN: llc -march=amdgcn -mcpu=SI --misched=si -mattr=si-scheduler < %s | FileCheck %s ; The test checks the "si" machine scheduler pass works correctly. @@ -11,45 +16,45 @@ ; CHECK: s_waitcnt vmcnt(0) ; CHECK: exp ; CHECK: s_endpgm - -define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, -<2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { +define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { main_body: - %22 = bitcast [34 x <8 x i32>] addrspace(2)* %3 to <32 x i8> addrspace(2)* - %23 = load <32 x i8>, <32 x i8> addrspace(2)* %22, align 32, !tbaa !0 - %24 = bitcast [17 x <4 x i32>] addrspace(2)* %2 to <16 x i8> addrspace(2)* - %25 = load <16 x i8>, <16 x i8> addrspace(2)* %24, align 16, !tbaa !0 - %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) - %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) - %28 = bitcast float %26 to i32 - %29 = bitcast float %27 to i32 - %30 = insertelement <2 x i32> undef, i32 %28, i32 0 - %31 = insertelement <2 x i32> %30, i32 %29, i32 1 - %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2) - %33 = extractelement <4 x float> %32, i32 0 - %34 = extractelement <4 x float> %32, i32 1 - %35 = extractelement <4 x float> %32, i32 2 - %36 = extractelement <4 x float> %32, i32 3 - %37 = call i32 @llvm.SI.packf16(float %33, float %34) - %38 = bitcast i32 %37 to float - %39 = call i32 @llvm.SI.packf16(float %35, float %36) - %40 = bitcast i32 %39 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40) + %tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)* + %tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0 + %tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)* + %tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0 + %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11) + %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11) + %tmp27 = bitcast float %tmp25 to i32 + %tmp28 = bitcast float %tmp26 to i32 + %tmp29 = insertelement <2 x i32> undef, i32 %tmp27, i32 0 + %tmp30 = insertelement <2 x i32> %tmp29, i32 %tmp28, i32 1 + %tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32> + %tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32> + %tmp31 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp30, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp32 = extractelement <4 x float> %tmp31, i32 0 + %tmp33 = extractelement <4 x float> %tmp31, i32 1 + %tmp34 = extractelement <4 x float> %tmp31, i32 2 + %tmp35 = extractelement <4 x float> %tmp31, i32 3 + %tmp36 = call i32 @llvm.SI.packf16(float %tmp32, float %tmp33) + %tmp37 = bitcast i32 %tmp36 to float + %tmp38 = call i32 @llvm.SI.packf16(float %tmp34, float %tmp35) + %tmp39 = bitcast i32 %tmp38 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp37, float %tmp39, float %tmp37, float %tmp39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 -; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } -!0 = !{!"const", null, i32 1} +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} |