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author | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
commit | dd58ef019b700900793a1eb48b52123db01b654e (patch) | |
tree | fcfbb4df56a744f4ddc6122c50521dd3f1c5e196 /test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll | |
parent | 2fe5752e3a7c345cdb59e869278d36af33c13fa4 (diff) | |
download | src-dd58ef019b700900793a1eb48b52123db01b654e.tar.gz src-dd58ef019b700900793a1eb48b52123db01b654e.zip |
Vendor import of llvm trunk r256633:
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=292915
Diffstat (limited to 'test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll new file mode 100644 index 000000000000..27a8e70aae13 --- /dev/null +++ b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -0,0 +1,16 @@ +; RUN: llc -o /dev/null %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos 2>&1 | FileCheck %s +; This test verifies that the instruction selection will add the implicit +; register operands in the correct order when modifying the opcode of an +; instruction to V_ADD_I32_e32. + +; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec + +define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %a = load i32, i32 addrspace(1)* %in + %b = load i32, i32 addrspace(1)* %b_ptr + %result = add i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} |