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| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
| commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
| tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/AMDGPU/fmul.ll | |
| parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
| download | src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.tar.gz src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.zip | |
Vendor import of llvm trunk r300422:vendor/llvm/llvm-trunk-r300422
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=317017
svn path=/vendor/llvm/llvm-trunk-r300422/; revision=317018; tag=vendor/llvm/llvm-trunk-r300422
Diffstat (limited to 'test/CodeGen/AMDGPU/fmul.ll')
| -rw-r--r-- | test/CodeGen/AMDGPU/fmul.ll | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/test/CodeGen/AMDGPU/fmul.ll b/test/CodeGen/AMDGPU/fmul.ll index d0c39b539456..125de7aabfd4 100644 --- a/test/CodeGen/AMDGPU/fmul.ll +++ b/test/CodeGen/AMDGPU/fmul.ll @@ -6,24 +6,20 @@ ; GCN: v_mul_f32 ; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W -define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { +define amdgpu_kernel void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { entry: %0 = fmul float %a, %b store float %0, float addrspace(1)* %out ret void } -declare float @llvm.r600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - ; FUNC-LABEL: {{^}}fmul_v2f32: ; GCN: v_mul_f32 ; GCN: v_mul_f32 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} -define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +define amdgpu_kernel void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fmul <2 x float> %a, %b store <2 x float> %0, <2 x float> addrspace(1)* %out @@ -40,7 +36,7 @@ entry: ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { +define amdgpu_kernel void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float>, <4 x float> addrspace(1) * %in %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr @@ -53,7 +49,7 @@ define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1) ; GCN: v_mul_f32 ; GCN-NOT: v_mul_f32 ; GCN: s_endpgm -define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { +define amdgpu_kernel void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 2.0 %z = fmul float %y, 3.0 store float %z, float addrspace(1)* %out @@ -65,7 +61,7 @@ define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { ; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mad_f32 ; GCN: s_endpgm -define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { +define amdgpu_kernel void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 3.0 %z = fmul float %y, 2.0 store float %z, float addrspace(1)* %out @@ -79,7 +75,7 @@ define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { ; GCN: v_mul_f32 ; GCN: v_mul_f32 ; GCN-NOT: v_mul_f32 -define void @test_mul_twouse(float addrspace(1)* %out, float %x, float %y) #0 { +define amdgpu_kernel void @test_mul_twouse(float addrspace(1)* %out, float %x, float %y) #0 { %a = fmul float %x, 5.0 %b = fsub float -0.0, %a %c = fmul float %b, %y |