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author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/AMDGPU/extractelt-to-trunc.ll | |
parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
download | src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.tar.gz src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.zip |
Vendor import of llvm trunk r300422:vendor/llvm/llvm-trunk-r300422
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=317017
svn path=/vendor/llvm/llvm-trunk-r300422/; revision=317018; tag=vendor/llvm/llvm-trunk-r300422
Diffstat (limited to 'test/CodeGen/AMDGPU/extractelt-to-trunc.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/extractelt-to-trunc.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/AMDGPU/extractelt-to-trunc.ll b/test/CodeGen/AMDGPU/extractelt-to-trunc.ll index e160c20a03a0..34999fa3aea4 100644 --- a/test/CodeGen/AMDGPU/extractelt-to-trunc.ll +++ b/test/CodeGen/AMDGPU/extractelt-to-trunc.ll @@ -7,7 +7,7 @@ ; GCN-DAG: buffer_load_dword [[A:v[0-9]+]] ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, [[B]], [[A]] ; GCN: buffer_store_dword [[ADD]] -define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { +define amdgpu_kernel void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { %a = load i64, i64 addrspace(1)* %in %add = add i64 %a, %b %val.bc = bitcast i64 %add to <2 x i32> @@ -20,7 +20,7 @@ define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspa ; GCN: buffer_load_dwordx2 ; GCN: v_add_f64 ; GCN: buffer_store_dword v -define void @bitcast_fp_to_vector_extract_0(i32 addrspace(1)* %out, double addrspace(1)* %in, double %b) { +define amdgpu_kernel void @bitcast_fp_to_vector_extract_0(i32 addrspace(1)* %out, double addrspace(1)* %in, double %b) { %a = load double, double addrspace(1)* %in %add = fadd double %a, %b %val.bc = bitcast double %add to <2 x i32> @@ -33,7 +33,7 @@ define void @bitcast_fp_to_vector_extract_0(i32 addrspace(1)* %out, double addrs ; GCN: buffer_load_dwordx2 ; GCN: v_add_i32 ; GCN: buffer_store_dword -define void @bitcast_int_to_fpvector_extract_0(float addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { +define amdgpu_kernel void @bitcast_int_to_fpvector_extract_0(float addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { %a = load i64, i64 addrspace(1)* %in %add = add i64 %a, %b %val.bc = bitcast i64 %add to <2 x float> @@ -45,7 +45,7 @@ define void @bitcast_int_to_fpvector_extract_0(float addrspace(1)* %out, i64 add ; GCN-LABEL: {{^}}no_extract_volatile_load_extract0: ; GCN: buffer_load_dwordx4 ; GCN: buffer_store_dword v -define void @no_extract_volatile_load_extract0(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +define amdgpu_kernel void @no_extract_volatile_load_extract0(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { entry: %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %elt0 = extractelement <4 x i32> %vec, i32 0 @@ -57,7 +57,7 @@ entry: ; GCN: buffer_load_dwordx4 ; GCN: buffer_store_dword v -define void @no_extract_volatile_load_extract2(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +define amdgpu_kernel void @no_extract_volatile_load_extract2(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { entry: %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %elt2 = extractelement <4 x i32> %vec, i32 2 @@ -68,7 +68,7 @@ entry: ; GCN-LABEL: {{^}}no_extract_volatile_load_dynextract: ; GCN: buffer_load_dwordx4 ; GCN: buffer_store_dword v -define void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { +define amdgpu_kernel void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { entry: %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %eltN = extractelement <4 x i32> %vec, i32 %idx |