src - FreeBSD source tree

diff options


context:
space:
mode:

author	Dimitry Andric <dim@FreeBSD.org>	2017-04-16 16:01:22 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2017-04-16 16:01:22 +0000
commit	71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch)
tree	5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/AMDGPU/ds_write2.ll
parent	31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff)
download	src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.tar.gz src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.zip

Vendor import of llvm trunk r300422:vendor/llvm/llvm-trunk-r300422

https://llvm.org/svn/llvm-project/llvm/trunk@300422

Notes

Notes: svn path=/vendor/llvm/dist/; revision=317017 svn path=/vendor/llvm/llvm-trunk-r300422/; revision=317018; tag=vendor/llvm/llvm-trunk-r300422

Diffstat (limited to 'test/CodeGen/AMDGPU/ds_write2.ll')

-rw-r--r--

test/CodeGen/AMDGPU/ds_write2.ll

1 files changed, 21 insertions, 21 deletions

diff --git a/test/CodeGen/AMDGPU/ds_write2.ll b/test/CodeGen/AMDGPU/ds_write2.ll
index ae230dac9378..ab1cf0ba25b5 100644
--- a/test/CodeGen/AMDGPU/ds_write2.ll
+++ b/test/CodeGen/AMDGPU/ds_write2.ll

@@ -9,7 +9,7 @@

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8

; SI: s_endpgm

-define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i

%val = load float, float addrspace(1)* %in.gep, align 4

@@ -27,7 +27,7 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8

; SI: s_endpgm

-define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i

%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1

@@ -46,7 +46,7 @@ define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1

; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}}

; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32

; SI: s_endpgm

-define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i

@@ -65,7 +65,7 @@ define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float

; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}}

; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32

; SI: s_endpgm

-define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i

@@ -86,7 +86,7 @@ define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float

; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8

; SI: s_endpgm

-define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i

%in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1

@@ -107,7 +107,7 @@ define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8

; SI: s_endpgm

-define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i

%val = load <2 x float>, <2 x float> addrspace(1)* %in.gep, align 8

@@ -126,7 +126,7 @@ define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x floa

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8

; SI: s_endpgm

-define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 %x.i

%val = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 16

@@ -146,7 +146,7 @@ define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x floa

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}

; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255

; SI: s_endpgm

-define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i

%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1

@@ -164,7 +164,7 @@ define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float

; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}

; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028

; SI: s_endpgm

-define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

+define amdgpu_kernel void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i

@@ -182,7 +182,7 @@ define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float add

; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8

; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0]], [[VAL1]] offset0:11 offset1:27

; SI: s_endpgm

-define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x

@@ -212,7 +212,7 @@ define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspac

; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8

; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0]], [[VAL1]] offset0:11 offset1:27

; SI: s_endpgm

-define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {

%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x

@@ -243,7 +243,7 @@ define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, f

; SI: ds_write_b32

; SI: s_endpgm

-define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 {

+define amdgpu_kernel void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i

%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i

@@ -270,7 +270,7 @@ define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float add

; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}

; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset1:8

; SI: s_endpgm

-define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i

%val = load double, double addrspace(1)* %in.gep, align 8

@@ -288,7 +288,7 @@ define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace

; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:1

; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15

; SI: s_endpgm

-define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {

+define amdgpu_kernel void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i

%val = load double, double addrspace(1)* %in.gep, align 8

@@ -306,7 +306,7 @@ define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, doubl

; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}

; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8

; SI: s_endpgm

-define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i

%in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1

@@ -325,7 +325,7 @@ define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace

; SI-LABEL: @store_constant_adjacent_offsets

; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}

; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1

-define void @store_constant_adjacent_offsets() {

+define amdgpu_kernel void @store_constant_adjacent_offsets() {

store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4

store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4

ret void

@@ -335,7 +335,7 @@ define void @store_constant_adjacent_offsets() {

; SI-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b{{$}}

; SI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}

; SI: ds_write2_b32 [[ZERO]], [[VAL]], [[VAL]] offset1:2

-define void @store_constant_disjoint_offsets() {

+define amdgpu_kernel void @store_constant_disjoint_offsets() {

store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4

store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4

ret void

@@ -348,7 +348,7 @@ define void @store_constant_disjoint_offsets() {

; SI-DAG: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1

; SI-DAG: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3

; SI: s_endpgm

-define void @store_misaligned64_constant_offsets() {

+define amdgpu_kernel void @store_misaligned64_constant_offsets() {

store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4

store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4

ret void

@@ -362,7 +362,7 @@ define void @store_misaligned64_constant_offsets() {

; SI-DAG: ds_write2_b32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1

; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1

; SI: s_endpgm

-define void @store_misaligned64_constant_large_offsets() {

+define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {

store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4

store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4

ret void

@@ -371,7 +371,7 @@ define void @store_misaligned64_constant_large_offsets() {

@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4

@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4

-define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 {

+define amdgpu_kernel void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1

%y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #1

%val = load float, float addrspace(1)* %in

@@ -410,7 +410,7 @@ define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, f

; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:3 offset1:2{{$}}

; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:1{{$}}

; CI: s_endpgm

-define void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 {

+define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 {

%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1

%in.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in

%val0 = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 4