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| author | Andrew Turner <andrew@FreeBSD.org> | 2018-11-01 17:43:28 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2018-11-01 17:43:28 +0000 |
| commit | a9725b6332be3242ea6601090f7f274354436fe6 (patch) | |
| tree | 73348c98660e3db73bcae348b092cd0f259e228f /sys | |
| parent | 5e6652144dcd70c1a3870ae2507be48ace75f8e8 (diff) | |
| download | src-a9725b6332be3242ea6601090f7f274354436fe6.tar.gz src-a9725b6332be3242ea6601090f7f274354436fe6.zip | |
Add the ARMv8.3 SCTLR_EL1 fields.
While here tag which architecture release fields were added and remove a
field that only existed in very early releases of the ARMv8 spec.
Sponsored by: DARPA, AFRL
Notes
Notes:
svn path=/head/; revision=340013
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arm64/arm64/locore.S | 2 | ||||
| -rw-r--r-- | sys/arm64/include/armreg.h | 21 |
2 files changed, 16 insertions, 7 deletions
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index 107d189618e4..f87a4d5bb59c 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -633,7 +633,7 @@ sctlr_set: sctlr_clear: /* Bits to clear */ .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ - SCTLR_ITD | SCTLR_THEE | SCTLR_A) + SCTLR_ITD | SCTLR_A) .globl abort abort: diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 05d504ca71ce..1ef9fdb5aeb8 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -525,7 +525,7 @@ #define PAR_S_MASK (0x1 << PAR_S_SHIFT) /* SCTLR_EL1 - System Control Register */ -#define SCTLR_RES0 0xc8222400 /* Reserved ARMv8.0, write 0 */ +#define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */ #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ #define SCTLR_M 0x00000001 @@ -534,23 +534,32 @@ #define SCTLR_SA 0x00000008 #define SCTLR_SA0 0x00000010 #define SCTLR_CP15BEN 0x00000020 -#define SCTLR_THEE 0x00000040 +/* Bit 6 is reserved */ #define SCTLR_ITD 0x00000080 #define SCTLR_SED 0x00000100 #define SCTLR_UMA 0x00000200 +/* Bit 10 is reserved */ +/* Bit 11 is reserved */ #define SCTLR_I 0x00001000 +#define SCTLR_EnDB 0x00002000 /* ARMv8.3 */ #define SCTLR_DZE 0x00004000 #define SCTLR_UCT 0x00008000 #define SCTLR_nTWI 0x00010000 +/* Bit 17 is reserved */ #define SCTLR_nTWE 0x00040000 #define SCTLR_WXN 0x00080000 -#define SCTLR_IESB 0x00200000 -#define SCTLR_SPAN 0x00800000 +/* Bit 20 is reserved */ +#define SCTLR_IESB 0x00200000 /* ARMv8.2 */ +/* Bit 22 is reserved */ +#define SCTLR_SPAN 0x00800000 /* ARMv8.1 */ #define SCTLR_EOE 0x01000000 #define SCTLR_EE 0x02000000 #define SCTLR_UCI 0x04000000 -#define SCTLR_nTLSMD 0x10000000 -#define SCTLR_LSMAOE 0x20000000 +#define SCTLR_EnDA 0x08000000 /* ARMv8.3 */ +#define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */ +#define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */ +#define SCTLR_EnIB 0x40000000 /* ARMv8.3 */ +#define SCTLR_EnIA 0x80000000 /* ARMv8.3 */ /* SPSR_EL1 */ /* |