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authorJake Burkholder <jake@FreeBSD.org>2001-11-18 04:00:22 +0000
committerJake Burkholder <jake@FreeBSD.org>2001-11-18 04:00:22 +0000
commit86f466074cbad745fd6d38fec2eb00e12b4f2a32 (patch)
tree1a8c362a504ff3436c92cdf5437a73a0411bb76d /sys/sparc64/include/fp.h
parentbf8f99b4b72fd2cb64f548ce737af92bd30b55e2 (diff)
downloadsrc-86f466074cbad745fd6d38fec2eb00e12b4f2a32.tar.gz
src-86f466074cbad745fd6d38fec2eb00e12b4f2a32.zip
1. Split fp.h into fp.h and fsr.h so that the latter can be included
in asm files. 2. Temporarily cause subnormal operands in floating point operations to be treated as zeros so that comlpetion of the operation does not need to be emulated. 3. Catch fp_exception_other and correctly skip over the unfinished instruction, but basically ignore them. Emulating the instruction is not yet supported. 4. Zero td_retval[1] as well in syscall(). Submitted by: tmm (2, 3)
Notes
Notes: svn path=/head/; revision=86530
Diffstat (limited to 'sys/sparc64/include/fp.h')
-rw-r--r--sys/sparc64/include/fp.h46
1 files changed, 8 insertions, 38 deletions
diff --git a/sys/sparc64/include/fp.h b/sys/sparc64/include/fp.h
index 699dba836ea9..ebb801f8ed0d 100644
--- a/sys/sparc64/include/fp.h
+++ b/sys/sparc64/include/fp.h
@@ -27,43 +27,6 @@
#ifndef _MACHINE_FP_H_
#define _MACHINE_FP_H_
-#define FPRS_DL (1 << 0)
-#define FPRS_DU (1 << 1)
-#define FPRS_FEF (1 << 2)
-
-#define FSR_CEXC_NX (1 << 0)
-#define FSR_CEXC_DZ (1 << 1)
-#define FSR_CEXC_UF (1 << 2)
-#define FSR_CEXC_OF (1 << 3)
-#define FSR_CEXC_NV (1 << 4)
-#define FSR_AEXC_NX (1 << 5)
-#define FSR_AEXC_DZ (1 << 6)
-#define FSR_AEXC_UF (1 << 7)
-#define FSR_AEXC_OF (1 << 8)
-#define FSR_AEXC_NV (1 << 9)
-#define FSR_QNE (1 << 13)
-#define FSR_NS (1 << 22)
-#define FSR_TEM_NX (1 << 23)
-#define FSR_TEM_DZ (1 << 24)
-#define FSR_TEM_UF (1 << 25)
-#define FSR_TEM_OF (1 << 26)
-#define FSR_TEM_NV (1 << 27)
-
-#define FSR_FCC0_SHIFT 10
-#define FSR_FCC0(x) (((x) >> FSR_FCC0_SHIFT) & 3)
-#define FSR_FTT_SHIFT 14
-#define FSR_FTT(x) (((x) >> FSR_FTT_SHIFT) & 7)
-#define FSR_VER_SHIFT 17
-#define FSR_VER(x) (((x) >> FSR_VER_SHIFT) & 7)
-#define FSR_RD_SHIFT 30
-#define FSR_RD(x) (((x) >> FSR_RD_SHIFT) & 3)
-#define FSR_FCC1_SHIFT 32
-#define FSR_FCC1(x) (((x) >> FSR_FCC1_SHIFT) & 3)
-#define FSR_FCC2_SHIFT 34
-#define FSR_FCC2(x) (((x) >> FSR_FCC2_SHIFT) & 3)
-#define FSR_FCC3_SHIFT 36
-#define FSR_FCC3(x) (((x) >> FSR_FCC3_SHIFT) & 3)
-
/* A block of 8 double-precision (16 single-precision) FP registers. */
struct fpblock {
u_long fpq_l[8];
@@ -75,8 +38,14 @@ struct fpstate {
u_long fp_fprs;
};
+#ifdef _KERNEL
+
+struct pcb;
+struct thread;
+
void fp_init_thread(struct pcb *);
-int fp_enable_thread(struct thread *);
+int fp_enable_thread(struct thread *, struct trapframe *);
+int fp_exception_other(struct thread *, struct trapframe *);
/*
* Note: The pointers passed to the next two functions must be aligned on
* 64 byte boundaries.
@@ -84,4 +53,5 @@ int fp_enable_thread(struct thread *);
void savefpctx(struct fpstate *);
void restorefpctx(struct fpstate *);
+#endif /* _KERNEL */
#endif /* !_MACHINE_FP_H_ */