Fix final bugs in memory barriers on PowerPC:

- Use isync/lwsync unconditionally for acquire/release. Use of isync
  guarantees a complete memory barrier, which is important for serialization
  of bus space accesses with mutexes on multi-processor systems.
- Go back to using sync as the I/O memory barrier, which solves the same
  problem as above with respect to mutex release using lwsync, while not
  penalizing non-I/O operations like a return to sync on the atomic release
  operations would.
- Place an acquisition barrier around thread lock acquisition in
  cpu_switchin().

1 files changed, 0 insertions, 5 deletions

diff --git a/sys/powerpc/include/atomic.h b/sys/powerpc/include/atomic.h
index c88c3fa39a58..8ec3ea0282b0 100644
--- a/sys/powerpc/include/atomic.h
+++ b/sys/powerpc/include/atomic.h
@@ -51,13 +51,8 @@
  * with the atomic lXarx/stXcx. sequences below. See Appendix B.2 of Book II
  * of the architecture manual.
  */
-#ifdef __powerpc64__
-#define __ATOMIC_REL()	__asm __volatile("lwsync" : : : "memory")
-#define __ATOMIC_ACQ()	__asm __volatile("lwsync" : : : "memory")
-#else
 #define __ATOMIC_REL()	__asm __volatile("lwsync" : : : "memory")
 #define __ATOMIC_ACQ()	__asm __volatile("isync" : : : "memory")
-#endif
 
 /*
  * atomic_add(p, v)