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| author | Rafal Jaworowski <raj@FreeBSD.org> | 2008-12-17 15:54:25 +0000 |
|---|---|---|
| committer | Rafal Jaworowski <raj@FreeBSD.org> | 2008-12-17 15:54:25 +0000 |
| commit | ece0de20a8dc64cbb7275642af590a13d95875d6 (patch) | |
| tree | 6c8b60e1427513daa91ac27cc6cfa2c6513965d4 /sys/powerpc/booke | |
| parent | fdd28cb88222b0f4f86806b64c61d8639a99c9fb (diff) | |
| download | src-ece0de20a8dc64cbb7275642af590a13d95875d6.tar.gz src-ece0de20a8dc64cbb7275642af590a13d95875d6.zip | |
Fix E500 cache invalidation routines.
When invalidating the i/d-cache we need to wait until the core complex is
really finished with the operation.
Obtained from: Semihalf
Notes
Notes:
svn path=/head/; revision=186230
Diffstat (limited to 'sys/powerpc/booke')
| -rw-r--r-- | sys/powerpc/booke/locore.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sys/powerpc/booke/locore.S b/sys/powerpc/booke/locore.S index 32f129b585e6..1f4ae661fc3e 100644 --- a/sys/powerpc/booke/locore.S +++ b/sys/powerpc/booke/locore.S @@ -411,6 +411,9 @@ ENTRY(dcache_inval) isync mtspr SPR_L1CSR0, %r3 isync +1: mfspr %r3, SPR_L1CSR0 + andi. %r3, %r3, L1CSR0_DCFI + bne 1b blr ENTRY(dcache_disable) @@ -443,6 +446,9 @@ ENTRY(icache_inval) isync mtspr SPR_L1CSR1, %r3 isync +1: mfspr %r3, SPR_L1CSR1 + andi. %r3, %r3, L1CSR1_ICFI + bne 1b blr ENTRY(icache_disable) |