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| author | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-03-23 05:31:35 +0000 |
|---|---|---|
| committer | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-03-23 05:31:35 +0000 |
| commit | 03ca7ae8a94b40e251a0cb628d999d87426a5501 (patch) | |
| tree | 4893027dd94d30451384445b5348d230052115f8 /sys/pci/if_rlreg.h | |
| parent | ce6283934ecd8cf04ef9eee88356024b270b1628 (diff) | |
| download | src-03ca7ae8a94b40e251a0cb628d999d87426a5501.tar.gz src-03ca7ae8a94b40e251a0cb628d999d87426a5501.zip | |
For MSI capable hardwares, enable MSI enable bit in RL_CFG2
register. If MSI was disabled by hw.re.msi_disable tunable
expliclty clear the MSI enable bit.
Notes
Notes:
svn path=/head/; revision=177522
Diffstat (limited to 'sys/pci/if_rlreg.h')
| -rw-r--r-- | sys/pci/if_rlreg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/pci/if_rlreg.h b/sys/pci/if_rlreg.h index d110df00643f..7e866891d14a 100644 --- a/sys/pci/if_rlreg.h +++ b/sys/pci/if_rlreg.h @@ -382,6 +382,7 @@ #define RL_CFG2_PCI66MHZ 0x01 #define RL_CFG2_PCI64BIT 0x08 #define RL_CFG2_AUXPWR 0x10 +#define RL_CFG2_MSI 0x20 /* * Config 3 register |