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authorYoshihiro Takahashi <nyan@FreeBSD.org>2002-01-06 09:54:50 +0000
committerYoshihiro Takahashi <nyan@FreeBSD.org>2002-01-06 09:54:50 +0000
commit26449b8fd7f531ac3b6c1e3cfd45751516b4277d (patch)
tree9082ceae6462a05e936602b65a012b0a0923f23d /sys/pc98/cbus/sio.c
parent3af626e4c676467a771f78b38a2d072ac77a2db2 (diff)
downloadsrc-26449b8fd7f531ac3b6c1e3cfd45751516b4277d.tar.gz
src-26449b8fd7f531ac3b6c1e3cfd45751516b4277d.zip
Merged from sys/dev/sio/sio.c revisions 1.354 and 1.358.
Notes
Notes: svn path=/head/; revision=88955
Diffstat (limited to 'sys/pc98/cbus/sio.c')
-rw-r--r--sys/pc98/cbus/sio.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/sys/pc98/cbus/sio.c b/sys/pc98/cbus/sio.c
index dcf0fa3b9fb6..e90704d9fe2a 100644
--- a/sys/pc98/cbus/sio.c
+++ b/sys/pc98/cbus/sio.c
@@ -3308,9 +3308,14 @@ comparam(tp, t)
* latencies are reasonable for humans. Serial comms
* protocols shouldn't expect anything better since modem
* latencies are larger.
+ *
+ * We have to set the FIFO trigger point such that we
+ * don't overflow it accidently if a serial interrupt
+ * is delayed. At high speeds, FIFO_RX_HIGH does not
+ * leave enough slots free.
*/
com->fifo_image = t->c_ospeed <= 4800
- ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
+ ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
#ifdef COM_ESP
/*
* The Hayes ESP card needs the fifo DMA mode bit set
@@ -4375,6 +4380,7 @@ siocnputc(dev, c)
dev_t dev;
int c;
{
+ int need_unlock;
int s;
struct siocnstate sp;
Port_t iobase;
@@ -4384,13 +4390,16 @@ siocnputc(dev, c)
else
iobase = siocniobase;
s = spltty();
- if (sio_inited)
+ need_unlock = 0;
+ if (sio_inited == 2 && !mtx_owned(&sio_lock)) {
mtx_lock_spin(&sio_lock);
+ need_unlock = 1;
+ }
siocnopen(&sp, iobase, comdefaultrate);
siocntxwait(iobase);
outb(iobase + com_data, c);
siocnclose(&sp, iobase);
- if (sio_inited)
+ if (need_unlock)
mtx_unlock_spin(&sio_lock);
splx(s);
}