Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core,

which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG.  This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores.  As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints.  UART instances appear in /dev
as ttyu0, ttyu1, etc.

However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues.  We work around
these as best we can, using various heuristics.

While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.

Sponsored by:	DARPA, AFRL

1 files changed, 3 insertions, 0 deletions

diff --git a/sys/mips/beri/files.beri b/sys/mips/beri/files.beri
index 2b302fcc32db..9bd5ee29173a 100644
--- a/sys/mips/beri/files.beri
+++ b/sys/mips/beri/files.beri
@@ -1,4 +1,7 @@
 # $FreeBSD$
+dev/altera/jtag_uart/altera_jtag_uart_cons.c	optional altera_jtag_uart
+dev/altera/jtag_uart/altera_jtag_uart_tty.c	optional altera_jtag_uart
+dev/altera/jtag_uart/altera_jtag_uart_nexus.c	optional altera_jtag_uart
 mips/beri/beri_machdep.c		standard
 mips/mips/intr_machdep.c		standard
 mips/mips/tick.c			standard