diff options
author | Marcel Moolenaar <marcel@FreeBSD.org> | 2006-05-12 23:24:45 +0000 |
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committer | Marcel Moolenaar <marcel@FreeBSD.org> | 2006-05-12 23:24:45 +0000 |
commit | ace86f3f275d811038495d84292148522966750f (patch) | |
tree | 3a18ede6d8065b47ad6c58db4266ca2a2d8aaa46 /sys/dev/uart/uart_dev_z8530.c | |
parent | cb9dec9ec145889fcf6607418b395ba6511e450b (diff) | |
download | src-ace86f3f275d811038495d84292148522966750f.tar.gz src-ace86f3f275d811038495d84292148522966750f.zip |
o A divisor of 0 is perfectly valid. Reserve -1 for an invalid
divisor. This allows us to set the line speed to the maximum
of 1/4 of the device clock.
o Disable the baudrate generator before programming the line
settings, including baudrate, and enable it afterwards.
Notes
Notes:
svn path=/head/; revision=158504
Diffstat (limited to 'sys/dev/uart/uart_dev_z8530.c')
-rw-r--r-- | sys/dev/uart/uart_dev_z8530.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/sys/dev/uart/uart_dev_z8530.c b/sys/dev/uart/uart_dev_z8530.c index c34b0a451fc0..bcde32f10287 100644 --- a/sys/dev/uart/uart_dev_z8530.c +++ b/sys/dev/uart/uart_dev_z8530.c @@ -68,11 +68,11 @@ z8530_divisor(int rclk, int baudrate) int act_baud, divisor, error; if (baudrate == 0) - return (0); + return (-1); divisor = (rclk + baudrate) / (baudrate << 1) - 2; if (divisor < 0 || divisor >= 65536) - return (0); + return (-1); act_baud = rclk / 2 / (divisor + 2); /* 10 times error in percent: */ @@ -80,7 +80,7 @@ z8530_divisor(int rclk, int baudrate) /* 3.0% maximum error tolerance: */ if (error < -30 || error > 30) - return (0); + return (-1); return (divisor); } @@ -117,11 +117,17 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, default: return (EINVAL); } - /* Set baudrate. */ if (baudrate > 0) { divisor = z8530_divisor(bas->rclk, baudrate); - if (divisor == 0) + if (divisor == -1) return (EINVAL); + } else + divisor = -1; + + uart_setmreg(bas, WR_MCB2, MCB2_PCLK); + uart_barrier(bas); + + if (divisor >= 0) { uart_setmreg(bas, WR_TCL, divisor & 0xff); uart_barrier(bas); uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); @@ -134,6 +140,8 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, uart_barrier(bas); uart_setmreg(bas, WR_TPC, tpc); uart_barrier(bas); + uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); + uart_barrier(bas); *tpcp = tpc; return (0); } @@ -157,9 +165,9 @@ z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, break; } uart_barrier(bas); - /* Set clock sources and enable BRG. */ + /* Set clock sources. */ uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); - uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); + uart_setmreg(bas, WR_MCB2, MCB2_PCLK); uart_barrier(bas); /* Set data encoding. */ uart_setmreg(bas, WR_MCB1, MCB1_NRZ); |